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ASIC Physical Design Senior Manager

Synopsys
August 09, 2026
Full-time
On-site
Hyderabad, Telangana, India
Physical Design Jobs, Level - Senior

Job Title

ASIC Physical Design Senior Manager

Role Summary

Lead and manage a physical design engineering team responsible for UCIe PHYs and testchip implementations at advanced process nodes. Deliver synthesis, place-and-route, timing closure, physical verification, DFT, and ATPG for production silicon while coordinating with cross-functional and customer teams.

Experience Level

Senior β€” requires substantial hands-on experience. The posting specifies 13+ years of ASIC physical design experience.

Responsibilities

Accountable for technical delivery, team leadership, and cross-functional alignment for UCIe PHY and testchip projects.

  • Lead physical design implementation across advanced nodes (5nm and below).
  • Own synthesis, place-and-route, timing closure, physical verification, DFT, and ATPG workflows.
  • Manage, mentor, and scale a team of physical design engineers; set priorities and ensure delivery.
  • Drive collaboration with verification, DFT, IP integration, and customer engineering to meet PPA and schedule goals.
  • Represent the physical design team in customer engagements and handle technical escalations.
  • Champion adoption of new tools, flows, and methodologies to improve productivity and quality.
  • Provide regular status updates to leadership, identify risks, and propose mitigations.

Requirements

Must-have technical skills and leadership experience. (Educational requirements are summarized separately below.)

  • 13+ years of hands-on ASIC physical design experience.
  • Multiple tapeouts and sign-offs at 5nm or more advanced process nodes.
  • Proficiency with industry tools such as Design Compiler (DC), PrimeTime (PT), ICC2/Finishing Compiler (ICC2/FC), and ICV.
  • Proven experience leading physical design teams and managing project timelines and deliveries.
  • Experience on SoC or IP tapeouts and interfacing with customers or internal stakeholders.
  • Strong understanding of FinFET technology and advanced-node physical design challenges.
  • Ability to represent engineering in business-unit or company-wide technical initiatives.

Education Requirements

Not specified.


About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.

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Date Posted: 2026-08-06