ASIC Physical Design & Implementation Lead

Job Title

ASIC Physical Design & Implementation Lead

Role Summary

Lead physical design for next-generation ASICs in the AECG ASIC organization, responsible for delivering signoff-quality RTL-to-GDSII implementations that meet power, performance and area (PPA) targets.

Work closely with customers, SoC architects, CAD and design teams to define and drive floorplanning and implementation flows for high-performance ASIC solutions.

Experience Level

Senior; typically requires 12+ years of professional experience in physical design and implementation for high-performance ASICs.

Responsibilities

Primary responsibilities include hands-on implementation, technical leadership, and flow development to achieve timing, power and area goals.

• Lead RTL-to-GDSII implementation and full-chip physical design flow.
• Define and execute floorplanning, power planning and pin/bus planning at chip level.
• Perform synthesis, placement, clock tree synthesis, timing optimization, routing and timing closure.
• Run parasitic extraction, static timing analysis, signoff-level verification (DRC/LVS) and crosstalk/EM/IR analysis.
• Ensure logical and physical equivalence and readiness for final signoff.
• Use and evaluate PNR and signoff tools (e.g. Fusion Compiler, ICC2, Innovus, Genus, PrimeTime, StarRC, Calibre, RedHawk).
• Identify complex technical problems, propose trade-offs and practical solutions.
• Drive automation and scripting to improve flow robustness and cycle time.
• Collaborate with geographically distributed teams and with customers to align implementation to requirements.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• 12+ years of hands-on physical design experience focused on high-performance designs.
• Strong background in physical design and timing analysis, with proven timing closure experience.
• Experience with automated synthesis and timing-driven place-and-route for high-speed datapaths and control logic.
• Experience with clock tree synthesis, clock/power gating, scan stitching, and design optimization for timing/power/area.
• Experience in floorplanning, IP integration, design methodology and final signoff for large IP/chip delivery.
• Proficiency scripting to automate design flows and improve productivity.
• Strong communication skills and ability to manage multiple projects concurrently.

Education Requirements

BS or MS degree in Electrical Engineering or Computer Science. The role expects substantial industry experience (example: 12+ years in physical design leading to comprehensive RTL-to-GDS implementation skills).

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.