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ASIC Physical Design Engineer (RDSS Intern)

NVIDIA
August 25, 2026
Internship
On-site
Hsinchu, Taiwan
Physical Design Jobs, Level - Entry or Early Career

Job Title

ASIC Physical Design Engineer (RDSS Intern)

Role Summary

Internship position on an ASIC physical design team working from RTL freeze through tape-out. The role focuses on synthesis, timing constraints, timing closure/sign-off, formal checks, and methodology/flow development for high-performance, low-power digital chips.

This position is part of NVIDIA's RDSS program and involves collaboration with ASIC, PR, and cross-functional teams to implement partitioning, floorplanning, and both pre- and post-layout timing closure.

Experience Level

Entry-level (Internship). Suitable for students or early-career candidates; typically 0–2 years of relevant hands-on IC implementation or academic project experience.

Responsibilities

Primary responsibilities include executing physical-design tasks across frontend and backend steps and improving automation and methodology.

  • Chip integration and netlist generation.
  • Synthesis and RTL/netlist quality checks.
  • Formal verification and constraints creation/validation; setting timing budgets.
  • Analyze and resolve special timing issues with ASIC and PR engineers.
  • Support chip partitioning, floorplan implementation, and full-chip timing closure.
  • Achieve timing closure for special modes (I/O, test, clock, async).
  • Create function ECOs and develop/improve timing-closure flows from pre-layout to post-layout.
  • Develop automation and methodology in the above areas.

Requirements

Key skills and attributes expected for candidates. Items marked "Nice-to-have" are not mandatory.

  • Project experience in IC design implementation (practical RTL-to-GDSII exposure preferred).
  • Proficient in English reading and writing.
  • Strong collaboration and debugging skills across design and verification teams.
  • Nice-to-have: Hands-on experience with EDA tools (Synopsys DC/PT/Formality, Cadence RC Compiler/LEC).
  • Nice-to-have: Scripting proficiency in Python or TCL for flow automation.

Education Requirements

MS in Electrical Engineering or Microelectronics is listed. Coursework in circuit design and digital design and project experience in IC design implementation are referenced. The posting does not specify allowance for equivalent experience.


About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.

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Date Posted: 2026-08-25