ASIC Physical Design Engineer (RDSS Intern)
Internship position on an ASIC physical design team working from RTL freeze through tape-out. The role focuses on synthesis, timing constraints, timing closure/sign-off, formal checks, and methodology/flow development for high-performance, low-power digital chips.
This position is part of NVIDIA's RDSS program and involves collaboration with ASIC, PR, and cross-functional teams to implement partitioning, floorplanning, and both pre- and post-layout timing closure.
Entry-level (Internship). Suitable for students or early-career candidates; typically 0β2 years of relevant hands-on IC implementation or academic project experience.
Primary responsibilities include executing physical-design tasks across frontend and backend steps and improving automation and methodology.
Key skills and attributes expected for candidates. Items marked "Nice-to-have" are not mandatory.
MS in Electrical Engineering or Microelectronics is listed. Coursework in circuit design and digital design and project experience in IC design implementation are referenced. The posting does not specify allowance for equivalent experience.
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.
