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ASIC Physical Design Engineer, Netlisting - New College Grad 2026

NVIDIA
August 16, 2026
Full-time
On-site
Santa Clara, California, United States
$116,000 - $218,500 USD yearly
Physical Design Jobs, Level - Entry or Early Career

Job Title

ASIC Physical Design Engineer, Netlisting - New College Grad 2026

Role Summary

Entry-level physical design engineer focusing on netlist integrity and tapeout readiness for high-frequency, low-power CPUs, GPUs and SoCs. The role works at block, cluster and full-chip levels to ensure correctness and manufacturability of synthesized netlists.

Experience Level

Entry-level (new college graduate). Suitable for recent Master's or PhD graduates or engineers with equivalent practical experience; typically 0–2 years of relevant experience.

Responsibilities

Work within the physical design and RTL teams to validate and prepare designs for tapeout; responsibilities include:

  • Perform equivalence checking and formal verification activities from RTL to netlist and through to tapeout.
  • Conduct asynchronous checks, including clock-domain-crossing (CDC) verification and MTBF analysis.
  • Execute and review logic synthesis and netlist quality checks at block and full-chip levels.
  • Support ECO generation and implementation to address timing, connectivity, and functional issues.
  • Collaborate with RTL/logic designers, timing engineers, and EDA tool teams to achieve timing closure.
  • Develop and maintain scripts and automation to support flows (Perl, TCL, Python, Make).
  • Debug netlist-related issues and participate in post-synthesis/tapeout problem resolution.

Requirements

Must-have technical skills and experience. Degree requirements are summarized separately under Education Requirements.

  • Demonstrated experience with logic equivalence checking and formal verification from RTL to tapeout using industry-standard tools.
  • Hands-on understanding of hardware architecture and RTL/logic design practices relevant to timing closure.
  • Experience with clock-domain-crossing checks and MTBF analysis using EDA or in-house tools.
  • Background in logic synthesis at block or full-chip level and experience executing or developing synthesis flows.
  • Familiarity with industry-standard EDA tools for synthesis, equivalence checking, and physical verification.
  • Proficiency in scripting and automation (Perl, TCL, Make, Python, or similar).
  • Preferred: strong debugging skills and experience improving workflows or productivity (AI-assisted methods are a plus).

Education Requirements

Master's or PhD in Electrical Engineering or Computer Engineering, or equivalent practical experience. (The source explicitly lists Master's or PhD in EE/CE with allowance for equivalent experience.)


About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.

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Date Posted: 2026-08-14