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ASIC Physical Design Engineer (Netlisting) — New College Grad 2026

NVIDIA
August 16, 2026
Full-time
On-site
Santa Clara, California, United States
$116,000 - $218,500 USD yearly
Physical Design Jobs, Level - Entry or Early Career

Job Title

ASIC Physical Design Engineer (Netlisting) — New College Grad 2026

Role Summary

Entry-level physical design engineer joining a team that supports netlist-focused signoff and implementation for high-performance CPUs, GPUs and SoCs. The role focuses on netlist quality, equivalence checking, asynchronous/clock-domain verification, synthesis interaction, and ECO implementation at block, cluster, and full-chip levels.

Experience Level

Entry-level / New college graduate (no specific years-of-experience required).

Responsibilities

Primary responsibilities center on netlist-related physical-design tasks and ECO work across block-to-chip scope.

  • Perform equivalence checking and formal verification workflows from RTL to tapeout.
  • Run asynchronous checks including clock-domain-crossing (CDC) verification and MTBF analysis.
  • Evaluate netlist quality and interact with logic synthesis results to support timing closure.
  • Develop and execute ECO (engineering change order) generation and implementation.
  • Collaborate with architecture, RTL, synthesis, and physical-design teams to resolve timing and functional issues.
  • Use and extend EDA tool flows and in-house tooling for netlist signoff tasks.

Requirements

Required technical skills and experience for immediate contribution; concise list of must-haves followed by differentiators.

  • Must-have: Practical experience with logic equivalence checking / formal verification flows from RTL to tapeout using industry-standard tools.
  • Understanding of hardware architecture and hands-on RTL/logic design relevant to timing closure.
  • Experience with clock-domain-crossing checks and MTBF analysis using EDA or in-house tools.
  • Background with logic synthesis at block or full-chip level and familiarity with synthesis flows.
  • Working knowledge of common EDA tools used for signoff and verification.
  • Proficiency in programming or scripting (examples: Perl, TCL, Make, Python).
  • Nice-to-have: Strong debugging/problem-solving skills; experience improving workflows or productivity through automation or AI-assisted tooling; additional exposure to full-chip signoff flows.

Education Requirements

Master's or PhD in Electrical Engineering or Computer Engineering, or equivalent practical experience. (Posting targets new college graduates 2026; equivalent experience accepted.)


About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.

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Date Posted: 2026-08-14