ASIC Physical Design Engineer II

Job Title

ASIC Physical Design Engineer II

Role Summary

Work on RTL-to-GDSII implementation for advanced process nodes (sub-16nm to 3nm) within Cisco's Silicon One hardware team. Focus on floorplanning, place-and-route, clock and power distribution, timing convergence, and cross-team coordination to deliver high-performance networking ASICs.

Collaborate with RTL, DFT, EDA vendors and tool owners to improve flows, debug timing issues, and standardize methodology across projects.

Experience Level

Mid-level (Engineer II). Hiring guidance: Master's degree holders may qualify with 0 years of professional experience; Bachelor's holders typically with ~2 years of relevant experience.

Responsibilities

Primary responsibilities include implementation and timing closure across the physical design flow.

• Lead RTL-to-GDSII implementation for advanced nodes (sub-16nm to 3nm).
• Define and execute hierarchical floorplanning, placement & routing, clock tree synthesis, and power distribution strategies.
• Perform static timing analysis, setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automation scripts for STA tools.
• Implement and manage timing ECO strategies and timing closure workflows.
• Analyze quality and efficiency gaps; recommend tool, flow, and methodology improvements.
• Collaborate with RTL, DFT, EDA vendors, and tool owners to drive design and implementation efficiency.
• Evaluate and adopt new timing methodologies and provide creative debugging solutions.
• Contribute to best practices and drive methodology alignment across projects.

Requirements

Required technical skills and experience; equivalent practical experience acceptable.

• Foundational knowledge of ASIC physical design and implementation flows (logic synthesis, placement, routing, timing closure).
• Understanding of floorplanning, clock tree synthesis, power distribution, and I/O planning.
• Proficiency in scripting (Python, Tcl, or Perl) for automation and data analysis.
• Hands-on experience with industry EDA tools (e.g., Cadence Innovus, Synopsys ICC2, Synopsys Design Compiler) via lab work, internships, or projects.
• Familiarity with physical verification (DRC/LVS) using tools such as Mentor Calibre or Synopsys ICV.
• Exposure to static timing analysis concepts and tools (e.g., PrimeTime) and timing ECO workflows.
• Ability to analyze tool and flow efficiency and propose improvements.

Education Requirements

Master's degree in a technical field (for example: ASIC physical design, electrical/computer engineering) with 0 years of professional experience, or a Bachelor's degree with approximately 2 years of relevant experience. Equivalent practical experience, academic projects, internships, or relevant coursework in ASIC design or related engineering disciplines is acceptable.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).