ASIC Physical Design Engineer
NVIDIAJob Title
ASIC Physical Design Engineer
Role Summary
Work on physical design (RTL to GDSII) for high-end ASICs on advanced process nodes. The role covers synthesis, constraints, STA/timing closure, partitioning, floorplan, and flow automation, collaborating with ASIC/P&R/DFT/SI/ARCH teams.
Experience Level
Entry / early-career. The team hires junior and senior engineers; this posting prefers candidates with around 1+ year experience.
Responsibilities
Core hands-on physical design and flow development responsibilities.
- Create and validate constraints for pre- and post-layout flows.
Requirements
Brief list of must-have and preferred skills; education details are in the Education Requirements section below.
- Must-have: Project experience in IC design implementation; proficient in English reading and writing.
- Preferred / Nice-to-have: Hands-on experience with EDA tools (Synopsys: Fusion Compiler/DC/PT/Formality; Cadence: RC Compiler/Genus/LEC).
- Preferred / Nice-to-have: Scripting proficiency (Python, Perl or TCL) for flow automation and methodology development.
- Preferred / Nice-to-have: DFT knowledge and experience with timing closure at chip scale.
Education Requirements
MS in Electrical Engineering, Computer Science, or Microelectronics is preferred with ~1+ year experience. Coursework in circuit design and digital design is expected. (No alternative-degree or "equivalent experience" language provided.)
About the Company
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.
