ASIC Physical Design Engineer

Job Title

ASIC Physical Design Engineer

Role Summary

Responsible for RTL-to-GDSII physical implementation of UCIe IP blocks on advanced process nodes (7nm/5nm/3nm). The role drives synthesis, floorplanning, power-grid architecture, placement, clock-tree synthesis, routing and sign-off while coordinating with front-end, verification and package teams.

Focus is on meeting strict latency, bandwidth and power targets for die-to-die interfaces and building automation to improve tape-out predictability.

Experience Level

Entry-level / Early Career — 1 to 3 years of ASIC physical design experience.

Responsibilities

Key responsibilities include ownership of the back-end implementation flow, closure to sign-off, and cross-team technical coordination.

• Lead RTL-to-GDSII implementation for UCIe IP: synthesis, floorplanning, power grid architecture, placement, clock tree synthesis, routing, and sign-off at 7nm/5nm/3nm.
• Close timing across multiple PVT corners and operating modes; optimize for latency and bandwidth of die-to-die interfaces.
• Perform physical and electrical verification using IC Validator; resolve DRC, LVS, ERC and mitigate electromigration, IR-drop, and signal integrity issues.
• Design and validate bump and pad ring patterns; coordinate with package teams on routing and pad/pin constraints.
• Build and maintain automation scripts in Python, Tcl, and Shell to streamline back-end flows and reduce cycle time.

Requirements

Must-have technical skills and tool experience.

• Practical RTL-to-GDSII ownership and tape-out experience on advanced nodes.
• Deep understanding of die-to-die interfaces (UCIe, HBM, high-speed DDR) and their timing, power, and signal-integrity constraints.
• Proficiency with Synopsys physical-design tools such as IC Compiler II or Fusion Compiler, PrimeTime, and IC Validator.
• Advanced scripting skills in Tcl and Python; familiarity with Shell scripting for automation.
• Experience addressing electrical issues (IR-drop, electromigration, signal integrity) during physical verification.
• Ability to work across time zones and collaborate with front-end designers, verification engineers, and package teams.

Nice-to-have:

• Prior work on chiplet architectures or die-to-die interface optimization.
• Experience creating reusable automated back-end methodology components.

Education Requirements

Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.