ASIC Physical Design Engineer

Job Title

ASIC Physical Design Engineer

Role Summary

Responsible for full-chip physical implementation and closure of ASIC/SoC designs for next-generation products. Work with cross-functional teams (RTL, verification, DFT, analog, packaging, product architecture) to deliver tapeout-ready designs.

Role emphasizes hands-on place-and-route execution, timing closure, signoff readiness, and automation of physical design flows.

Experience Level

Mid-level — typically requires 5+ years of hands-on ASIC physical design experience.

Responsibilities

Primary duties include implementing and closing digital physical designs and improving physical design flows.

• Implement ASIC physical design from RTL or gate-level netlist through GDSII: floorplanning, placement, CTS, routing, and closure.
• Run and optimize place-and-route flows with industry-standard EDA tools for timing, power, area, and signal integrity.
• Perform static timing analysis and resolve setup/hold/constraint issues across modes and corners.
• Support physical signoff activities: DRC, LVS, extraction, IR drop, electromigration, and signal integrity analyses.
• Collaborate with RTL, verification, DFT, analog, packaging, and product teams to resolve implementation issues and ensure manufacturability.
• Develop and maintain scripts, automated flows, documentation, and review materials to improve methodology and schedule predictability.

Requirements

Must-have technical skills and experience; followed by concise nice-to-have items.

• 5+ years of hands-on ASIC physical design experience from RTL to verified GDS.
• Practical experience with floorplanning, power planning, place-and-route, clock tree synthesis, routing, and design closure.
• Strong knowledge of RTL-to-GDSII flows and ability to resolve congestion, timing, power, area, and SI issues.
• Experience with static timing analysis, constraints, multi-mode multi-corner verification, and timing closure at block or SoC level.
• Familiarity with physical signoff checks and debug activities (DRC, LVS, extraction, equivalence checking, IR drop, electromigration, crosstalk).
• Proficiency with industry-standard physical design and timing tools (Cadence, Synopsys, Siemens EDA, or equivalent).
• Strong scripting and automation skills (Tcl, Python, Perl, or shell) to support flows, debug, and reporting.
• Ability to provide actionable feedback to RTL and packaging teams to improve hand-off quality.
• Basic knowledge of ECO practices.

Nice-to-haves:

• Experience leading physical design implementation for complex ASIC/SoC programs and managing external design service providers.
• Advanced expertise in timing methodology, ECO implementation, and driving signoff readiness at SoC or major-subsystem level.

Education Requirements

Bachelor's degree in Electrical Engineering preferred or equivalent practical experience. Advanced degrees (MS or PhD in Electrical Engineering) are listed as preferred. The posting allows equivalent experience in lieu of formal degrees.

About the Company

Company: Tektronix

Headquarters: Beaverton, OR, United States

Tektronix designs and manufactures electronic test and measurement equipment—oscilloscopes, signal generators, analyzers and related software—serving customers in telecommunications, aerospace, semiconductor and electronics industries.