ASIC Physical Design Engineer

Job Title

ASIC Physical Design Engineer

Role Summary

Lead the physical implementation of system-on-chip (SoC) designs, translating front-end architecture into tape-out-ready silicon. The role owns floorplanning, clock-tree synthesis, placement-and-routing optimization, sign-off verification, and physical debug for high-performance ASICs.

Work closely with architects, RTL teams, and verification to meet timing, power, and signal-integrity targets for advanced-node designs.

Experience Level

Senior — typically 8+ years of hands-on ASIC physical design experience; the posting requests 8–10+ years and expects full lifecycle tape-out ownership.

Responsibilities

Primary responsibilities include design planning, implementation, verification, and delivery of complex SoC physical designs.

• Define and validate pre-layout timing constraints to verify architectural feasibility.
• Architect block- and chip-level floorplans; optimize pin assignments and spatial layout.
• Plan and execute clock tree synthesis and review complex clock specifications.
• Optimize placement and routing to achieve timing, area, and power targets.
• Perform sign-off flows: RC extraction, static timing analysis (STA), and IR-drop mitigation.
• Resolve physical verification issues and debug sign-off failures to enable defect-free tape-outs.
• Automate flows and checks via scripting; produce technical summaries and presentations for stakeholders.

Requirements

Must-have technical skills and eligibility; nice-to-have items listed separately.

• Must-have: 8+ years of hands-on ASIC physical design experience with full project lifecycle ownership to tape-out.
• Must-have: Expert experience with advanced process nodes (example targets: 28nm, 16nm, and below).
• Must-have: Proficiency with industry physical-design and sign-off tools (examples: ICC2/Innovus; PrimeTime, Redhawk, or equivalents).
• Must-have: Strong scripting skills for automation (Tcl, Perl, or Python).
• Must-have: Demonstrated experience in STA, RC extraction, CTS, P&R optimization, IR-drop mitigation, and physical verification sign-off.
• Must-have: Currently authorized to work in the United States on a full-time, permanent basis (no visa sponsorship provided).
• Nice-to-have: Experience with hierarchical layout strategies and leading engineering in lean, high-impact teams.

Education Requirements

Bachelor of Science in Electrical Engineering (BSEE) required. Master of Science (MSEE) in integrated circuit design, semiconductor physics, or a related field is preferred.

About the Company

Company: StaffRight Associates

Technical staffing and recruiting firm that places engineering and technology professionals, including ASIC/semiconductor and related hardware roles. Focuses on matching experienced candidates to high-impact, full-time opportunities and supporting career growth through client partnerships.