ASIC Physical Design Engineer

Job Title

ASIC Physical Design Engineer

Role Summary

Join the Common Hardware Group designing high-performance networking ASICs (Cisco Silicon One). This role executes RTL-to-GDSII implementation for advanced process nodes and works across RTL, DFT, and EDA vendors to deliver production silicon.

Location: Austin, TX. Starting salary range for U.S./Canada new hires: $167,700–$245,200 (posted range).

Experience Level

Mid-level. Typical background: Bachelor's in Electrical Engineering plus ~5 years of relevant ASIC physical-design experience, Master’s plus ~2 years, or PhD with relevant experience. See Education Requirements for degree details.

Responsibilities

Accountable for end-to-end physical implementation and improving backend flows and methodologies.

• Own RTL-to-GDSII implementation for advanced nodes (sub-16nm down to 2nm).
• Define and execute hierarchical floorplanning, placement & routing, clock and power distribution, and timing-convergence strategies.
• Perform static timing analysis (STA), setup reviews, and sign-offs for multi-mode/multi-corner designs; automate STA flows and scripts.
• Implement and manage timing ECO strategies (e.g., using Prime Closure/PrimeTime) and debug timing issues.
• Analyze quality and efficiency gaps; recommend tool, flow, and methodology improvements.
• Collaborate with RTL, DFT, EDA vendors, and tool owners to drive implementation efficiency and methodology alignment.
• Evaluate and adopt new timing methodologies and provide practical debugging solutions.

Requirements

Core technical requirements and desirable skills. Degree and formal-education specifics are in Education Requirements below.

Must-have

• Hands-on ASIC physical design and implementation experience (RTL-to-GDSII).
• Experience with hierarchical floorplanning, clock and power distribution, global signal and I/O planning, and physical convergence/timing closure.
• Experience performing STA and timing closure for multi-mode/multi-corner designs.
• Power-integrity analysis experience and working on designs larger than 100M gates in advanced nodes (16nm, 14nm, 7nm, 5nm, 3nm, 2nm).
• Ability to analyze flows, develop automated scripts, and drive methodology improvements.

Nice-to-have

• Scripting experience (TCL, Python) and effective use of AI tools for automation.
• Place & Route experience with Cadence Innovus or Synopsys Fusion Compiler.
• Synthesis experience (Cadence Genus or Synopsys tools) and familiarity with formal verification tools (Synopsys Formality, Cadence LEC).
• Experience with PrimeTime (DMSA) for STA, Apache RedHawk/Voltus for power integrity, and Synopsys ICV or Mentor Calibre for physical verification.

Education Requirements

Bachelor's degree in Electrical Engineering (EE) with ~5 years related experience, or Master's degree in EE with ~2 years related experience, or PhD in EE with relevant experience. The posting allows equivalent practical experience in lieu of degrees. Fields referenced: Electrical Engineering (EE).

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).