ASIC Physical Design Apprenticeship

Job Title

ASIC Physical Design Apprenticeship

Role Summary

This is a 12-month, full-time in-office apprenticeship in ASIC physical design implementation. The apprentice will work on digital implementation tasks (floorplanning, synthesis, timing, verification) and support physical verification and DFM activities under the guidance of experienced engineers.

Location: Noida, India. Start date: April/May 2026. The role provides hands-on project experience with industry-standard Synopsys tools and workflows.

Experience Level

Entry-level apprenticeship/internship suitable for recent graduates and early-career candidates (0–1 years of professional experience).

Responsibilities

Hands-on implementation and verification of ASIC physical design tasks; collaborate with engineering team to develop and optimize flows.

• Participate in the digital implementation flow: floor-planning, timing constraints, physical synthesis, and formal verification.
• Contribute to clock tree optimization, routing, extraction, and timing closure for mixed-signal IP and subsystems.
• Support design-for-test (DFT), signal integrity analysis, and physical verification/DFM on test-chips across technology nodes.
• Develop and optimize implementation flows; debug issues and improve automation alongside experienced engineers.
• Gain practical experience using Synopsys toolchains and apply methodologies to real projects.

Requirements

Eligibility and technical skills required for successful participation in the apprenticeship.

• Must-have: Good knowledge of digital logic, high-speed clocks and timing, and signal integrity.
• Must-have: Strong scripting skills (Perl, Tcl, or Python).
• Must-have: Understanding of CMOS/FINFET design/layouts and low-power design techniques.
• Must-have: Familiarity with IC design and physical implementation flows.
• Eligibility: Not employed in any full-time position (limited internship experience acceptable).
• Nice-to-have: Experience with Synopsys tools (Design Compiler, ICC/ICC2/FC, PrimeTime SI, Star-RCXT, RedHawk, ICV) and knowledge of deep-submicron technology.

Education Requirements

B.E. / B.Tech in Electronics, Electrical, Instrumentation, ECE, EEE, VLSI, or a related technical field. Candidates should be fresh graduates from the class of 2024 or 2025 only; not currently enrolled in M.Tech programs or postgraduate diplomas. Limited internship experience is acceptable; equivalent practical experience is not specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.