ASIC NPI Support Engineer

Job Title

ASIC NPI Support Engineer

Role Summary

Senior engineer responsible for end-to-end technical support of ASIC new-product-introduction (NPI) projects from backend physical implementation through tapeout, wafer fabrication, packaging and silicon bring-up to mass-production ramp.

Works with design teams, foundries, packaging houses and internal process/PDK/IP teams to resolve cross-stage technical risks and improve first-pass silicon success rates.

Experience Level

Senior — the posting requests at least 8 years of relevant ASIC physical design, tapeout and NPI experience.

Responsibilities

Provide technical leadership across ASIC NPI stages and manage multiple concurrent projects to ensure on-time tapeout and production readiness.

• Lead technical support for the full ASIC NPI lifecycle: backend reviews, DFM checks, tapeout preparation, foundry handoff, wafer and package tracking, and post-silicon validation.
• Conduct pre-tapeout reviews of floorplan, P&R results, power grid, physical verification (DRC/LVS/ERC), antenna and DFM issues.
• Troubleshoot tapeout/release, mask, wafer and packaging issues; collaborate with foundry/process engineers on yield analysis.
• Support silicon bring-up and correlate post-silicon failures with layout/process; perform root-cause analysis and recommend re-spin solutions.
• Establish and maintain NPI checklists, DFM rules and tapeout SOPs to improve first-pass silicon yield.
• Collect customer NPI feedback and coordinate internal teams (backend, PDK, IP, process) to resolve escalations.
• Organize technical workshops and compile failure case studies to provide proactive guidance for customer projects.
• Track project milestones and manage schedules under high-pressure tapeout timelines.

Requirements

Must-have technical skills and experience to perform the role.

• At least 8 years of hands-on experience in ASIC physical design, tapeout and silicon validation, including bring-up, characterization and production ramp.
• Proven experience across full backend flow: floorplan, placement, CTS, routing, timing closure, power integrity and physical signoff using tools such as ICC2/Innovus, PrimeTime, StarRC and Calibre.
• Deep knowledge of DFM, multi-patterning, antenna effects, EM/IR signoff and physical verification closure prior to tapeout.
• Familiarity with foundry PDK release flow, mask data preparation (MDP), GDS release requirements, and wafer & packaging processes.
• Experience in post-silicon failure analysis, layout-process correlation and re-spin root-cause investigation.
• Strong problem-solving skills across design, layout, process and test domains and excellent project coordination under tapeout schedules.
• Fluent written and spoken English for global customer communication and cross-fab coordination.

Nice-to-have:

• Experience with advanced process nodes (e.g., 7nm/5nm) or mature nodes (28nm/14nm) and packaging/3D IC integration.
• Hands-on foundry customer engineering or tapeout/design service NPI roles.
• Proficiency in Tcl/Python scripting for automation and pre-tapeout checks.

Education Requirements

Bachelor's degree or higher (B.S./M.S./Ph.D.) in Microelectronics, Electrical/Electronics Engineering, Computer Engineering, Integrated Circuit Design or a related technical field. The posting lists degree-plus-experience alternatives (example: Bachelor's +4 years, Master's +3 years, PhD +2 years) and also allows equivalent practical experience.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.