ASIC NPI Support Engineer

Job Title

ASIC NPI Support Engineer

Role Summary

Lead technical support for ASIC New Product Introduction (NPI) across backend physical implementation, tapeout, wafer fabrication, packaging and post-silicon bring-up. Coordinate with foundries, packaging vendors and internal design teams to remove manufacturability risks and enable successful first-pass silicon and mass production ramps.

Experience Level

Senior role. The posting requests extensive hands-on NPI and backend experience — typically 8+ years in ASIC physical design, tapeout and silicon validation.

Responsibilities

Provide end-to-end technical ownership during ASIC NPI and support customers through tapeout to production.

• Lead technical reviews across floorplan, P&R results, power grid, physical verification (DRC/LVS/ERC) and DFM before tapeout.
• Prepare and validate tapeout deliverables, mask data preparation (MDP) and GDS release requirements.
• Troubleshoot tapeout, mask, wafer processing and packaging issues; work with foundry process engineers to identify yield-limiting factors.
• Support silicon bring-up and post-silicon test failure correlation, perform root-cause analysis and recommend revisions for re-spin.
• Establish and maintain NPI checklists, DFM rules and tapeout standard operating procedures to improve first-pass silicon success rate.
• Coordinate cross-functional teams (backend, PDK, IP, process) to resolve escalated technical bottlenecks.
• Organize technical workshops and compile case studies on yield and failure modes for customer guidance.
• Track project milestones and manage multiple concurrent NPI projects to meet tapeout and production ramp schedules.

Requirements

Must-have technical skills and experience for successful performance in this role.

• At least 8 years' experience covering ASIC physical design, tapeout and NPI silicon validation; hands-on silicon bring-up, characterization and production readiness.
• Practical experience across full backend flow: floorplan, placement, CTS, routing, timing closure, power integrity and physical signoff.
• Experience with EDA tools such as ICC2/Innovus, PrimeTime, StarRC and Calibre.
• In-depth knowledge of DFM, multi-patterning, antenna effects, EM/IR signoff and physical verification closure.
• Familiarity with foundry PDK release processes, mask data preparation (MDP) and semiconductor packaging processes.
• Proven post-silicon failure analysis experience and layout-process correlation for chip re-spin investigations.
• Strong problem-solving, project coordination and ability to manage high-pressure tapeout schedules.
• Fluent written and spoken English for global customer communication and cross-fab coordination.

Education Requirements

Required: Bachelor's degree or above in Microelectronics, Electrical/Electronics Engineering, Integrated Circuit Design, Computer Engineering or a related technical field. The posting also specifies degree-plus-experience alternatives: Bachelor's + 4+ years, Master's + 3+ years, or PhD + 2+ years of relevant Hardware Applications Engineering or Hardware Design experience. Advanced degrees (MS/PhD) are accepted; specific certifications are not mentioned.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.