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ASIC Implementation Engineer - Static Verification

Meta Platforms
June 29, 2026
Full-time
On-site
Sunnyvale, California, United States
$114,000 - $172,000 USD yearly
ASIC Design Jobs, Level - Mid-Career

Job Title

ASIC Implementation Engineer - Static Verification

Role Summary

Join Meta's Infrastructure engineering organization to perform front‑end ASIC implementation and static verification for SoC and IP used in data center applications. The role covers RTL linting, clock- and reset-domain verification, RTL DFT analysis, synthesis to gate-level netlist, and automation of front-end flows.

Experience Level

Mid-level — typically requires around 2+ years of experience in static verification and front‑end ASIC flows.

Responsibilities

Work with design and verification teams to ensure correct and optimized front-end implementation from RTL to netlist.

  • Perform flat and hierarchical Clock Domain Crossing (CDC) analysis and sign-off, working with designers to resolve complex CDC issues.
  • Perform Reset Domain Crossing (RDC) checks and define reset groups and reset sequences in coordination with design and firmware teams.
  • Run RTL lint checks and work with designers to create and manage waivers.
  • Perform RTL DFT analysis and improve stuck‑at fault coverage.
  • Run logic/physical synthesis with advanced optimizations and generate optimized gate‑level netlists for timing, area, and power tradeoffs.
  • Develop automation scripts and front-end methodology for lint, CDC, RDC and related tools.
  • Support handoff tasks and provide timing and congestion feedback to physical design, DV, and emulation teams.

Requirements

Must-have technical skills and experience; preferred items are listed as nice-to-have.

  • Must-have: ~2+ years experience using static verification tools and front-end ASIC flows.
  • Experience with lint tools, CDC and RDC analysis, and SOC CDC sign-off.
  • Knowledge of SoC integration topics (clocking, reset architectures, PLLs) and front-end implementation.
  • Experience with RTL design using SystemVerilog or other HDLs.
  • Ability to communicate and collaborate across design, verification, emulation, and vendor teams.
  • Nice-to-have: familiarity with Design Compiler, Spyglass, PrimeTime, Formality, or equivalent tools.
  • Experience scripting in Perl/Python, TCL, and Make; developing checks for RTL and netlist; and improving MTBF through Netlist-CDC analysis.
  • Knowledge of timing/physical libraries and SRAM memories; experience with SoC design integration.

Education Requirements

Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field — or equivalent practical experience. The posting specifies the degree must be completed prior to joining Meta.


About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.

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Date Posted: 2026-06-28