ASIC Implementation Engineer STA

Job Title

ASIC Implementation Engineer STA

Role Summary

Responsible for full-chip static timing analysis and timing sign-off to ensure the ASIC meets performance and timing requirements across all process, voltage, and temperature (PVT) corners. Owns constraint development, timing closure, and delivery of timing ECOs while collaborating with RTL, Physical Design, and DFT teams.

Experience Level

Senior — requires a minimum of 12 years of hands-on ASIC STA and timing-closure experience.

Responsibilities

Primary responsibilities include timing sign-off, constraint management, and automation:

• Own full-chip timing sign-off and quality checks across PVT corners and sign-off modes.
• Author, validate, and maintain SDC constraints for functional and test modes (Scan, MBIST, ATPG).
• Analyze foundry guidelines and incorporate sign-off corners, margins, and derates into STA flows.
• Manage Multi-Mode Multi-Corner (MMMC) analyses and hundreds of timing scenarios.
• Develop and automate timing ECOs to fix setup, hold, and transition violations.
• Apply advanced timing concepts such as AOCV/POCV, crosstalk, and IR-drop aware STA.
• Script and automate analysis flows and data mining using Tcl, Python, and Perl.
• Collaborate with cross-functional teams to resolve complex timing issues and define guard-banding.
• Document best practices and lessons learned to improve timing methodology.

Requirements

Must-have technical skills and experience:

• Minimum of 12 years of hands-on ASIC STA and timing-closure experience using Cadence or Synopsys sign-off tools.
• Expertise in timing closure, on-chip variation derates, and optimizing multi-mode multi-corner constraints.
• High proficiency in scripting for automation: Tcl (primary), Python, and Perl; Shell scripting experience helpful.
• Deep knowledge of AOCV/POCV, signal integrity (crosstalk), and IR-drop aware STA.
• Experience generating and implementing timing ECOs and automating those flows.
• Strong problem-solving skills and clear, precise communication; able to work effectively in teams.
• Expert proficiency with industry-standard sign-off EDA tools.

Nice-to-have:

• Prior experience interpreting foundry sign-off guidelines at scale.
• Experience driving power/performance/area trade-offs into implementation flows.

Education Requirements

Bachelor's degree in Electrical Engineering or Computer Engineering.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.