ASIC Implementation Engineer
BroadcomJob Title
ASIC Implementation Engineer
Role Summary
Work on top-level physical implementation for ASIC products, focusing on floorplanning, partitioning, clock delivery and tape-out for next-generation AI and PCIe switch designs. Collaborate with design, packaging and methodology teams to integrate blocks, plan I/O/bump placement, and resolve chip-level physical-design issues.
Experience Level
Senior-level. Hiring guidance in the posting indicates candidates with substantial experience in top-level floorplanning (examples: 8+ years with a Bachelor’s degree or 6+ years with a Master’s degree).
Responsibilities
Primary responsibilities for the role include ownership of top-level physical implementation and cross-team coordination during integration and tape-out.
- Own chip floorplanning, partition creation, and top-level clock tree and delivery.
- Estimate die size, perform partitioning and pin planning for top-level integration.
- Resolve physical-design issues related to chip integration, assembly, and advanced-node DRC/LVS/EMIR where applicable.
- Coordinate I/O and bump planning with the package team and manage top-level bump/RDL considerations.
- Develop and improve floorplan implementation methodologies using industry and internal tools.
- Perform technical evaluations of vendors and IP and provide recommendations to meet design specifications.
Requirements
Must-have technical skills and constraints; preferred skills are listed separately.
- Proven experience in top-level floorplanning, clocking and partitioning for complex ASICs.
- Track record resolving chip-integration physical issues and working with advanced-node physical verification flows.
- Experience collaborating with design, package and methodology teams throughout development.
- Familiarity with EDA tools and scripting (examples: Python, Tcl, Perl) for implementation and automation.
- Work must be performed on-site at Broadcom's San Jose location; remote work is not available.
- Nice-to-have: experience with SerDes, HBM, high-speed DDR, chiplets/D2D I/O, bump planning, RDL implementation, hierarchical floorplanning, power grid design, and multi-voltage domain designs.
Education Requirements
Posting specifies: Bachelor’s degree in Electrical Engineering with 8+ years of relevant top-level floorplanning experience, or Master’s degree in Electrical Engineering with 6+ years of relevant experience.
About the Company
Company: Broadcom
Headquarters: Irvine, California, United States
Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.
