ASIC/FPGA Verification Engineer (UVM / SystemVerilog) — Onsite

Job Title

ASIC/FPGA Verification Engineer (UVM / SystemVerilog) — Onsite

Role Summary

Work on verification of ASICs and FPGAs using SystemVerilog and UVM. Implement self-checking testbenches, coverage models, and verification flows; support FPGA bring-up and hardware integration.

Position is onsite in Mountain View, CA; first shift, typical hours approximately 8:00 AM–5:00 PM.

Experience Level

Mid-level. Posting references both 2+ years (associate) and 5+ years (experienced) verification experience as guidance.

Responsibilities

Primary verification and integration tasks:

• Write SystemVerilog/UVM testbenches for ASIC and FPGA verification.
• Develop reusable, self-checking UVM components: drivers, monitors, sequencers, scoreboards.
• Build functional coverage models and address code/coverage gaps.
• Create tests for DSP and third-party IP integration.
• Run simulations, linting, CDC checks, static timing checks, and gate-level regressions.
• Automate verification flows using scripting (Python/Perl/Make) and revision control (git/svn).
• Support FPGA bring-up, hardware emulation/prototyping, and hardware integration testing.
• Collaborate with system and hardware teams to capture requirements and debug issues.

Requirements

Must-have technical skills and experience:

• Hands-on ASIC/FPGA verification experience using SystemVerilog and UVM.
• Ability to build self-checking, object-oriented SystemVerilog testbenches.
• Familiarity with functional coverage and code coverage closure techniques.
• Comfortable working in Linux and using scripting tools to automate flows.
• Experience with simulation, linting, CDC/static timing checks, and gate-level regression flows.
• Experience using revision control systems (git or svn).

Nice-to-have:

• Experience with hardware emulators (e.g., Palladium) and FPGA prototyping.
• Knowledge of high-speed SerDes protocols (PCIe, Ethernet, JESD204C).
• Experience with SystemVerilog Assertions (SVA) and RTL-to-GDS flows.
• Familiarity with space/radiation mitigation techniques.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field; equivalent practical experience is acceptable.

About the Company

Company: Indotronix Avani Group

Engineering services firm providing FPGA/ASIC design and verification support for high‑reliability and military systems (e.g., GPS). Offers contract engineering across requirements capture, digital architecture, RTL design (VHDL/Verilog), verification (SystemVerilog/UVM), timing closure, and lab integration in secure environments.