ASIC/FPGA Verification Engineer (UVM / SystemVerilog)

Job Title

ASIC/FPGA Verification Engineer (UVM / SystemVerilog)

Role Summary

Onsite verification engineer responsible for functional verification of ASICs and FPGAs using SystemVerilog and UVM. Works with system and hardware teams to develop testbenches, automate verification flows, and support FPGA bring-up and prototyping.

Experience Level

Mid-level. Preferred experience guidance: 2+ years for associate-level or 5+ years for experienced verification engineers.

Responsibilities

Primary duties include developing verification infrastructure, executing verification flows, and collaborating with cross-functional teams to debug and integrate hardware.

• Write SystemVerilog/UVM testbenches and self-checking UVM components (drivers, monitors, scoreboards, sequencers).
• Develop functional coverage models and close code-coverage gaps.
• Create tests to verify DSP and third-party IP integration.
• Run simulations, linting, CDC checks, static timing analysis, and gate-level regressions.
• Automate flows using scripting (Python/Perl/Make) and revision control (git/svn).
• Support FPGA bring-up, hardware emulation/prototyping, and hardware integration tests.
• Collaborate with system and hardware teams to capture requirements and debug issues.

Requirements

Must-have technical skills and tools; preferred items listed separately.

• Experience with ASIC/FPGA verification using SystemVerilog and UVM.
• Ability to build self-checking testbenches and use object-oriented SystemVerilog features.
• Familiarity with functional coverage and code-coverage closure.
• Comfortable in Linux and competent with scripting to automate verification tasks.
• Experience with simulation, linting, CDC checks, and gate-level regression workflows.
• Experience with revision control systems (git or svn).

Nice-to-have:

• Experience with hardware emulators (e.g., Palladium) and FPGA prototyping.
• Knowledge of high-speed SerDes protocols (PCIe, Ethernet, JESD204C).
• Experience with SystemVerilog Assertions (SVA) and RTL-to-GDS flows.
• Familiarity with space/radiation mitigation techniques.
• 2+ years (Associate) or 5+ years (Experienced) verification experience.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field — or equivalent practical experience.

About the Company

Company: Indotronix Avani Group

Engineering services firm providing FPGA/ASIC design and verification support for high‑reliability and military systems (e.g., GPS). Offers contract engineering across requirements capture, digital architecture, RTL design (VHDL/Verilog), verification (SystemVerilog/UVM), timing closure, and lab integration in secure environments.