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ASIC/FPGA Verification Engineer (UVM / SystemVerilog)

Indotronix Avani Group
June 29, 2026
Full-time
On-site
Mountain View, California, United States
Verification Jobs, Level - Mid-Career

Job Title

ASIC/FPGA Verification Engineer (UVM / SystemVerilog)

Role Summary

Verify ASIC and FPGA designs by developing SystemVerilog/UVM testbenches, coverage models, and verification flows. Work with hardware, system, and IP teams to validate DSP and third‑party IP integration and support FPGA bring‑up and hardware prototyping.

Experience Level

Mid-level. Candidates with ~2+ years (associate) or ~5+ years (experienced) verification experience preferred.

Responsibilities

Key responsibilities include:

  • Write SystemVerilog/UVM testbenches and develop self‑checking, reusable UVM components (drivers, monitors, scoreboards, sequencers).
  • Build functional coverage models and close code coverage gaps.
  • Create tests to verify DSP and third‑party IP integration.
  • Run simulations, linting, CDC checks, static timing checks, and gate‑level regressions.
  • Automate verification flows using scripting (Python/Perl/Make) and revision control (git/svn).
  • Support FPGA bring‑up, hardware emulation/prototyping, and hardware integration tests.
  • Collaborate with system and hardware teams to capture requirements and debug issues.

Requirements

Must-have skills and technologies:

  • Proven ASIC/FPGA verification experience using SystemVerilog and UVM.
  • Ability to build self‑checking testbenches and use object‑oriented SystemVerilog features.
  • Familiarity with functional coverage and code coverage closure.
  • Comfortable working in Linux and using scripting tools and version control.
  • Experience with simulation and verification flows (simulation, lint, CDC, STA, gate‑level regression).

Nice-to-have:

  • Experience with hardware emulators (e.g., Palladium) and FPGA prototyping.
  • Knowledge of high‑speed SerDes (PCIe, Ethernet, JESD204C) and SVA.
  • Experience with RTL‑to‑GDS flows and space/radiation mitigation techniques.
  • 2+ years (Associate) or 5+ years (Experienced) verification experience.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.


About the Company

Company: Indotronix Avani Group

Engineering services firm providing FPGA/ASIC design and verification support for high‑reliability and military systems (e.g., GPS). Offers contract engineering across requirements capture, digital architecture, RTL design (VHDL/Verilog), verification (SystemVerilog/UVM), timing closure, and lab integration in secure environments.

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Date Posted: 2026-06-29