ASIC/FPGA Verification Engineer 5 - UVM
CTS InternationalJob Title
ASIC/FPGA Verification Engineer 5 - UVM
Role Summary
Lead verification engineer responsible for SystemVerilog/UVM verification of ASIC and FPGA designs on critical programs. Drives verification strategy, debug, and coverage closure while coordinating technical activities across the product lifecycle.
This is a 100% onsite role in El Segundo, CA and requires an active Secret clearance to start.
Experience Level
Senior - expects 7+ years of verification experience (5+ acceptable with strong UVM expertise); demonstrated ability to lead technical work and make architectural decisions.
Responsibilities
Key responsibilities include:
- Design and implement SystemVerilog/UVM verification environments and self-checking testbenches.
- Develop verification plans and verification strategies; drive coverage closure.
- Debug complex RTL and verification failures; perform root-cause analysis.
- Lead technical aspects of proposal preparation and support supplier/vendor technical evaluations.
- Coordinate verification and engineering activities across the product lifecycle.
- Recommend and manage technology insertion and develop concepts for future designs.
- Produce clear technical documentation and mentor less-experienced engineers.
Requirements
Must-have:
- Secret clearance required to start.
- Strong SystemVerilog and UVM expertise with significant hands-on verification experience (7+ years preferred; 5+ acceptable with solid UVM).
- Proven experience with self-checking, constrained-random verification and coverage-driven methodologies.
- Strong debugging skills for RTL and verification environments; experience closing coverage gaps.
- Ability to work independently, exercise sound engineering judgment, and communicate clearly.
- Available to work onsite in El Segundo, CA for the assignment duration.
Nice-to-have:
- ASIC and FPGA design/verification background.
- Experience leading supplier/vendor technical interactions or contributing to technical proposals.
Education Requirements
Typical education: advanced technical degree in Engineering, Computer Science, Mathematics, Physics, or Chemistry (e.g., Bachelor's). The posting lists experience-equivalents such as Bachelor + ~14 years, Master + ~12 years, PhD + ~9 years; ABET accreditation preferred. Equivalent practical experience may be acceptable.
About the Company
Company: CTS International
Headquarters: El Segundo, CA, USA
CTS International provides engineering staffing, workforce solutions, and technical services for defense, aerospace, and advanced technology programs, supplying cleared talent and program support across the product lifecycle.
