ASIC Engineering Technical Leader - Design Verification

Job Title

ASIC Engineering Technical Leader - Design Verification

Role Summary

Lead verification efforts for high-performance ASIC/SoC designs on the Cisco SiliconOne team. Own DV architecture, testbenches, verification flows and cross-functional coordination from RTL simulation through emulation and silicon bring-up.

Work closely with Architecture, Design, Emulation, Software and post-silicon validation teams to define verification strategy and deliverable quality.

Experience Level

Senior - requires substantial industry experience (see Education Requirements for years guidance).

Responsibilities

Primary responsibilities include:

• Define and build UVM/SystemVerilog testbenches and verification infrastructure from scratch or extend existing environments with a focus on reuse.
• Define or improve DV methodologies and drive adoption across projects.
• Perform end-to-end verification of one or more blocks and support full-chip integration and system-level validation.
• Plan, generate, review and execute test plans to meet ASIC group criteria.
• Develop emulation infrastructure (C/C++) that interfaces with UVM-based verification environments.
• Run gate-level simulations and SDF back-annotation as part of pre-silicon verification.
• Collect, merge and analyze code and functional coverage; work with designers to close coverage holes.
• Participate across RTL verification, emulation and post-silicon validation phases.
• Lead technical decisions, conduct DV meetings and syncs with stakeholders, and drive code reviews and postmortems.
• Mentor and lead engineers to ensure timely, high-quality deliverables and reusable solutions.

Requirements

Must-have:

• Extensive hands-on experience with SystemVerilog and UVM methodology; delivered UVM-based infrastructure in multiple projects.
• Proven ability to handle complex chip features independently and drive technical decisions at program level.
• Proficient in collecting, merging and analyzing simulation coverage data and driving coverage closure.
• Good working knowledge of C and C++ with debugging skills for emulation and bring-up.
• Experience with system debug, SW/HW bring-up and silicon validation toward FCS.
• Experience with hardware emulation platforms and tools (examples: EVE, Veloce).
• Strong leadership, communication and collaboration skills; experience leading and mentoring engineers.

Preferred:

• Experience defining DV strategies and planning verification architecture for large-scale, high-performance ASICs.
• Experience leading test plan reviews and driving complex system-level debug and integration.
• Experience with flow automation (scripting, Makefiles) and establishing team guidelines.

Education Requirements

BS or MS degree. The posting specifies approximately 12+ years of hands-on ASIC design verification experience for candidates with a BS, or ~10+ years with an MS.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).