ASIC Engineering Design Verification Leader (SystemVerilog, Python, C, UVM)

Job Title

ASIC Engineering Design Verification Leader (SystemVerilog, Python, C, UVM)

Role Summary

Lead functional verification for silicon-photonics based optical transceivers and modules (pluggable and co-packaged optics) within Cisco’s Client Optics Group. Work across block, subsystem and full-chip verification to define methodology, develop UVM testbenches, and drive pre- and post-silicon validation.

The role requires close collaboration with RTL, firmware, FPGA and test-engineering teams to validate high-speed IPs (SerDes, ODSP, D2D PHY, Ethernet) and to prepare designs for production testing.

Experience Level

Senior - 8–12 years of functional verification experience (as stated in the posting).

Responsibilities

Accountable for defining and executing verification tasks from block to SoC level and supporting post-silicon bring-up.

• Create verification plans, develop testbench components and define verification methodology.
• Design and implement UVM components (agents, drivers, monitors, scoreboards, sequences) and verification environments.
• Develop constrained-random and directed tests, functional coverage models, and assertions.
• Run block- and full-chip simulations with integrated high-speed IPs (ODSP, SerDes, D2D PHY, integrated transceivers) and debug failures.
• Execute verification scenarios that include CPU firmware; verify CPU sub-system interactions and firmware-driven functionality.
• Support FPGA-based verification where required.
• Participate in post-silicon ATE test plan development, test-vector generation and release-to-production activities.
• Analyze coverage data, add scenarios/corner cases to improve coverage, and drive resolution of functional bugs.

Requirements

Core technical skills and experience required for the role.

Must-have:

• 8–12 years of functional verification experience (block through full-chip).
• Strong SystemVerilog and UVM methodology skills, including familiarity with UVM phases, configuration, factory overrides and reuse.
• Proficiency in Python and C for testbench scripting, automation, and firmware-level verification.
• Experience with RTL design, simulation tools and standard ASIC design flow (Synopsys/Cadence/Mentor toolchains).
• Understanding of high-speed interfaces and IPs: SerDes (including PAM4), ODSP, D2D PHY, integrated transceiver features, and Ethernet protocols.
• Knowledge of DFT principles and practical debug/problem-solving skills.
• Ability to work collaboratively across teams and drive decisions with consensus.

Nice-to-have:

• Experience with CPU sub-systems, firmware-driven verification, and FPGA-based validation.
• Prior exposure to ATE test plan development and production test vector creation.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering or a related/ equivalent technical discipline; or equivalent practical experience as specified in the posting.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).