ASIC Engineer, Power

Job Title

ASIC Engineer, Power

Role Summary

The ASIC Engineer, Power will develop and maintain power analysis and optimization flows used across Meta's silicon teams. The role sits at the intersection of EDA tooling, physical design, and power methodology to model, estimate, and reduce power in custom ASIC designs.

Experience Level

Mid-level. The posting requests candidates with roughly 6+ years of relevant ASIC/physical design experience focused on power analysis and signoff.

Responsibilities

Key responsibilities include building, operating, and improving power analysis infrastructure and collaborating with design teams to achieve power closure.

• Develop and maintain dynamic and static power estimation flows, vectorless analysis, and power intent verification.
• Define and implement power methodology for RTL, synthesis, and physical design stages.
• Collaborate with RTL, physical design, and verification teams to identify and mitigate power hotspots.
• Build and optimize EDA automation and infrastructure scripts to improve signoff accuracy and turnaround time.
• Evaluate and integrate commercial and internal EDA tools into power flows.
• Create and verify power intent specifications (UPF/CPF) across RTL-to-GDSII flows.
• Establish power budgets, track metrics across milestones, and report results and risks to stakeholders.
• Drive continuous improvement of power-closure methodologies across tape-outs.
• Provide technical guidance and partner with EDA vendors to influence tool capabilities.

Requirements

Must-have technical skills and experience for performing the role; preferred items follow separately.

Must-have:

• 6+ years of ASIC or physical design experience with a focus on power analysis, optimization, or signoff.
• Experience developing or maintaining power analysis EDA flows using tools such as Synopsys PrimePower or Cadence Voltus (or equivalent).
• Practical experience with UPF or CPF for power intent and applying them across RTL-to-GDSII flows.
• Scripting experience (Python, Tcl, or shell) to build and automate EDA workflows.
• Proven collaboration across RTL design, physical design, and verification to drive power closure on complex ASICs.

Nice-to-have:

• Experience evaluating and qualifying new EDA tools or methodologies in production silicon environments.
• Familiarity with custom or semi-custom flows for high-performance or data-center silicon.
• Experience with low-power techniques: clock gating, power gating, multi-voltage domains, DVFS.
• Background in building internal EDA infrastructure or flow automation at scale.

Education Requirements

Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.