ASIC Engineer, Implementation - Timing

Job Title

ASIC Engineer, Implementation - Timing

Role Summary

Join Meta's Silicon Engineering team to drive the physical implementation of custom ASICs from RTL through tapeout with a focus on timing. The role covers synthesis, static timing analysis (STA), timing closure, and signoff while collaborating with architecture, design, verification, and physical design teams.

Experience Level

Mid-level. The posting specifies 6+ years of experience in timing analysis and ASIC implementation.

Responsibilities

Work across front-end and back-end flows to ensure timing closure and deliver optimized gate-level netlists that meet PPA targets.

• Develop timing constraints for RTL-to-synthesis and PrimeTime STA for blocks and top-level SOC, including inter-block IO budgets.
• Create SOC full-chip flat and hierarchical timing constraints for functional and DFT modes.
• Perform STA for full chip and physical partition blocks using PrimeTime or equivalent tools.
• Run logic and physical synthesis using advanced optimization techniques to generate gate-level netlists optimized for timing, area, and power.
• Develop automation scripts and methodology for front-end tools (synthesis, STA) to improve productivity and repeatability.
• Collaborate with design, verification, emulation, and physical design teams; provide timing and congestion feedback during handoff and integration.

Requirements

Key technical must-haves and valuable additional skills.

• Must-have: 6+ years of experience in timing analysis and ASIC implementation focusing on timing closure.
• Must-have: Experience developing full-chip flat and hierarchical timing constraints.
• Must-have: Experience with AOCV/POCV timing analysis and signal-integrity (SI) noise analysis.
• Must-have: Experience running full-chip static timing analysis using DMSA or equivalent methodologies.
• Must-have: Practical knowledge of front-end (RTL, synthesis) and back-end (place & route, timing closure) ASIC flows and cross-team communication.
• Nice-to-have: Experience with SoC design integration and front-end implementation.
• Nice-to-have: Familiarity with back-end PD tools such as Fusion Compiler or Innovus, and front-end synthesis tools such as Design Compiler or Genus.
• Nice-to-have: Experience building automation using scripting languages (Tcl, Python) for synthesis/STA flows.

Education Requirements

Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.