ASIC Engineer, Implementation (Low-Power Design)

Job Title

ASIC Engineer, Implementation (Low-Power Design)

Role Summary

Engineer on Meta's Silicon Engineering team focused on turning RTL into power-efficient silicon for data center and AI workloads. The role concentrates on power modeling, low-power implementation techniques, and flows spanning synthesis through signoff.

Work with architecture, RTL, verification, emulation, and vendor teams to meet aggressive performance, power, and area (PPA) targets.

Experience Level

Entry-level — expects approximately 2+ years of relevant industry experience in modeling, scripting, or implementation.

Responsibilities

Deliver low-power implementation and estimation capabilities across abstraction levels and coordinate with cross-functional teams.

• Define system- and module-level power specifications for idle, typical, and TDP scenarios.
• Develop power modeling infrastructure and architectural simulators (Python/C++).
• Build power estimation flows at C-model, RTL, gate, and layout levels.
• Apply leakage and dynamic power analysis to assess environment and process impacts.
• Evaluate and implement low-power techniques (clock gating, power gating, multi-voltage domains) across design stages.
• Collaborate with RTL designers to resolve timing, area, and power issues early.
• Participate in design reviews and influence architectural/microarchitectural tradeoffs.
• Perform power characterization and debug on silicon; work with vendors and EDA partners on interfaces and estimation tools.

Requirements

Must-have technical skills and tools experience; preferred items listed separately.

• 2+ years experience with modeling and design using C++, Python, or an equivalent high-level language.
• Experience with industry-standard EDA tools for synthesis and physical implementation (examples: Synopsys Design Compiler, Cadence Genus, Innovus, ICC-2).
• Experience with scripting for flow automation and data analysis (Tcl, Python, Perl, or similar).
• Practical knowledge of ASIC design processes, including leakage and dynamic power estimation and closure considerations.
• Ability to collaborate across HW/SW co-design, architecture, design verification, emulation, and vendor teams.

Nice-to-have:

• RTL design experience (SystemVerilog or other HDL).
• Formal verification or equivalence checking experience in RTL-to-GDS flows.
• Post-silicon bringup and cross-abstraction debugging experience (emulator, RTL, silicon).
• Background in data center or AI accelerator ASIC development and system-level performance/power modeling.

Education Requirements

Bachelor's degree in Computer Engineering, Computer Science, or Electrical Engineering, or equivalent practical experience. Preferred: Master's degree in the same fields or equivalent practical experience.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.