Senior Layout Design Engineer

Job Title

Senior Layout Design Engineer

Role Summary

Senior physical-layout engineer on the Foundation IP team in Ho Chi Minh City. Responsible for creating and optimizing custom layouts for embedded memory, standard cells, and IO to meet performance, power, density, and manufacturability targets.

Works cross-functionally with circuit designers and verification to ensure successful tape-outs and to improve layout methodology and automation across process nodes.

Experience Level

Senior — role title indicates senior level. The posting requests 2+ years of hands-on custom IC layout experience.

Responsibilities

Key responsibilities include delivering and improving physical layouts and layout flows for Foundation IP.

• Design and develop custom layouts for embedded memory IPs, standard cells, and IO structures using industry-standard layout tools.
• Optimize layout topologies for density, performance, power, and manufacturability across advanced process nodes.
• Collaborate with circuit designers and verification teams to meet electrical and physical design requirements.
• Debug and resolve DRC, LVS, and antenna violations in complex hierarchical designs.
• Develop and refine layout methodologies and automation flows to improve efficiency across the IP portfolio.
• Participate in design reviews and document layout guidelines, design decisions, and process updates.

Requirements

Must-have technical skills and experience; followed by useful but optional qualifications.

• Must-have: 2+ years hands-on experience in custom IC layout design focused on memory compilers, standard cells, or analog/mixed-signal blocks.
• Must-have: Deep understanding of layout fundamentals including device matching, parasitic extraction, electromigration, and IR drop.
• Must-have: Proficiency with industry layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or equivalent.
• Must-have: Solid grasp of DRC/LVS verification flows and ability to debug complex rule violations.
• Must-have: Strong documentation and communication skills for cross-functional collaboration.
• Nice-to-have: Experience developing layout methodologies and automation flows; experience with advanced process nodes and Foundation IP portfolios.
• Nice-to-have: Track record of improving layout development efficiency and enabling first-pass silicon success.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Telecommunication, Physics, or a related technical field (as stated in the posting).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.