ASIC Engineer, Implementation - CAD

Job Title

ASIC Engineer, Implementation - CAD

Role Summary

Meta's Infrastructure Silicon team is hiring an ASIC Implementation (CAD) Engineer to develop and maintain CAD methodologies, flows, and automation supporting RTL through physical design signoff for data-center chips.

The role partners with design, physical design, verification, architecture, and vendor teams to enable efficient, high-quality tape-outs and to drive floorplanning, connectivity analysis, and PPA improvements.

Experience Level

Mid-level. The posting requests approximately 2+ years of relevant experience in synthesis and physical design.

Responsibilities

Primary responsibilities include building production CAD platforms, data models, and automation to accelerate implementation and analysis.

• Design, develop and maintain production CAD platforms and web-based design tooling for architecture exploration, floorplan visualization, and automated engineering analysis.
• Build runtime-optimized data models, algorithms and Python APIs for large-scale design data (netlist, LEF/DEF, pin/track, connectivity) to improve performance over native EDA tools.
• Develop tooling for SOC floorplans at chip, subsystem, and block level; drive early floorplan exploration, block shaping, and area/dimension estimation.
• Implement debug features for logical and physical connectivity and beachfront analysis on DEF and netlist data; evaluate pin locations, port configurations, and connectivity consistency.
• Develop automation and methodology across front-end and back-end tools (synthesis, physical design, STA, power, floorplanning, connectivity analysis, pin planning) and collaborate on handoffs and timing/congestion/connectivity feedback.

Requirements

Must-have technical skills and experience.

• 2+ years of experience in synthesis and physical design.
• Proficiency in Python for algorithm development, engineering analysis, and automation.
• Experience developing CAD/EDA tools, flows, or engineering automation.
• Experience with RTL synthesis, physical design and PPA optimization, and familiarity with front-end and back-end ASIC tools.
• Experience collaborating with cross-functional teams and external vendors to debug timing, area, and power issues.

Nice-to-have:

• Experience with DEF, netlists, floorplanning data, pin definition generation and PG-aware pin placement across hierarchical partitions.
• Strong software engineering fundamentals: data structures, algorithms, computational geometry, and performance optimization on large datasets.
• Experience with multi-chiplet connectivity, feedthrough evaluation, clock/voltage/reset domains and 2.5D/3D SoIC assembly.
• Experience writing parsers and data models for Verilog netlist, LEF/DEF, Liberty, SDC.
• Experience building web-based engineering applications with interactive visualization and client-server architecture.

Education Requirements

Bachelor's degree in Computer Science, Computer Engineering or a relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.