ASIC Engineer, Foundry and IP

Job Title

ASIC Engineer, Foundry and IP

Role Summary

Join the Infrastructure Silicon team to evaluate foundry technologies, optimize foundation IP (standard cells, memory compilers), and deliver high-performance, power-efficient ASIC building blocks. The role collaborates with foundry partners, physical design, and test-chip teams to drive PPA (power, performance, area) tradeoffs and validate IP through test chips.

Experience Level

Mid-level / Mid-Career - typically requires 6+ years of relevant ASIC/foundry experience.

Responsibilities

Deliver technical leadership across foundry benchmarking, IP evaluation, and test-chip execution.

• Analyze and benchmark foundry process options with physical design teams to guide technology choices.
• Run early PPA evaluations of foundation IP via preliminary PnR experiments and transistor-level simulations.
• Architect, design, and characterize high-performance, low-power, and high-density standard cell libraries with foundry partners.
• Evaluate and select third-party memory compilers (SRAM, register files, ROM) based on PPA trade-offs.
• Perform SPICE-level simulations, custom layout work, and manage automated library characterization flows.
• Participate in physical implementation and tape-out of silicon test chips to validate new IP and custom structures.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• 6+ years driving foundry PPA analysis and benchmarking in a foundry or equivalent team setting.
• Deep understanding of CMOS device physics, digital circuit design, and advanced-node layout constraints.
• Proven hands-on experience owning end-to-end partition design and sign-off on test chips (tapeout experience).
• Expert-level use of design and simulation tools such as Cadence Virtuoso, HSPICE, Spectre.
• Working knowledge of synthesis, place-and-route (PnR), static timing analysis (STA), and physical design verification (PDV) tools.
• High proficiency in scripting/automation (Python, TCL, Perl, SKILL) to build large-scale evaluation pipelines and analyze results.
• Nice-to-have: experience as a chip lead, DTCO optimization with foundry partners, and driving PPA selection/optimization for standard cells and memory compilers.
• Nice-to-have: experience delivering sub-5nm, 3nm, or 2nm GAA test chips and complex advanced-node validation.

Education Requirements

Minimum: Bachelor's degree in Computer Science, Computer Engineering, or a related technical field - or equivalent practical experience. Preferred: MS or PhD in Electrical Engineering. The posting explicitly allows equivalent practical experience in lieu of a degree.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.