ASIC Engineer

Job Title

ASIC Engineer

Role Summary

Member of a flows/methodology team focused on improving RTL quality, sign-off methodology, and readiness for silicon. The role connects digital implementation and microarchitecture with CDC, RDC, RTL-NA/DA, PSI, lint, and related structural checks.

Work spans methodology development, technical analysis, tool evaluation and deployment, and cross-team coordination with RTL, CAD, verification and physical teams to improve predictability and project outcomes.

Experience Level

Mid-level — typically requires 3+ years of ASIC or SoC RTL design or design-methodology experience.

Responsibilities

The engineer will develop and deploy RTL design-quality methodologies and drive their adoption across projects.

• Develop and deploy RTL-quality methodologies (CDC, RDC, Netlist/Design Auditors, power insertion, lint, structural checks).
• Analyze flow results in the context of design intent and perform detailed root-cause analysis across RTL, constraints, tools, and methodology.
• Define quality requirements and readiness criteria; monitor regressions, violation trends, and sign-off status.
• Collaborate with RTL build, DFT, clocks/reset, low-power, physical-design, verification, and CAD teams to resolve technical issues.
• Assess new tool releases and methodology capabilities and coordinate their integration into project environments.
• Improve runtime, debugging efficiency, waiver management, reporting, and training through automation and reusable scripts.

Requirements

Must-have technical skills and experience.

• 3+ years of experience in ASIC or SoC RTL design or design-methodology.
• Practical experience with Verilog or SystemVerilog build, analysis, and debugging.
• Solid knowledge of digital design and microarchitecture: pipelines, FSMs, clock/reset architectures, synchronizers, handshakes, asynchronous FIFOs, metastability, and power-domain crossings.
• Experience with front-end methodologies such as lint, CDC/RDC, structural RTL analysis, low-power verification, synthesis, or timing constraints.
• Ability to relate methodology results to RTL behavior and perform detailed root-cause analysis.
• Experience with Linux development environments and scripting in Python, Tcl, Perl, shell, or a comparable language.

Nice-to-have:

• Experience with RTL integration, design bring-up, or multi-team debugging at unit, subsystem, chiplet, or SoC level.
• Familiarity with tools such as Meridian, SpyGlass, VC CDC, Questa CDC, Design Auditor, or power-insertion tools.
• Knowledge of UPF and low-power RTL implementation or verification.
• Experience with SDC, synthesis, static timing analysis, formal verification, or equivalence checking.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.