ASIC Engineer - Early Career

Job Title

ASIC Engineer - Early Career

Role Summary

Entry-level ASIC engineer contributing to RTL design and verification of digital blocks inside larger SoCs. Multiple early-career positions available across engineering teams and primary locations; placement will depend on candidate skills and business needs.

The role emphasizes learning industry-standard verification methodologies while supporting module- and subsystem-level verification, debug, and integration activities under senior engineering guidance.

Experience Level

Entry-level / Early Career — suitable for recent graduates or candidates in their final year.

Responsibilities

Typical duties include design and verification tasks for digital ASIC/SoC blocks and supporting verification closure.

• Contribute to Verilog/SystemVerilog RTL design and verification of digital blocks within larger SoCs.
• Support module-level and subsystem-level verification using SystemVerilog/UVM.
• Write test plans and functional coverage definitions under guidance from senior engineers.
• Assist with CDC/RDC/LINT checks and remediation activities.
• Participate in code coverage and functional coverage closure activities.
• Develop assertions, protocol monitors, and scoreboards for testbenches.
• Support integration and verification of external IP (bus fabrics, standard interfaces).
• Debug RTL and testbench issues with guidance from senior engineers.
• Document design intent, verification results, and test coverage.

Requirements

Must-have technical skills, workplace expectations, and legal eligibility.

• Coursework or project experience with Verilog/SystemVerilog RTL design or verification.
• Understanding of digital logic fundamentals: combinational/sequential logic, FSMs, timing.
• Familiarity with verification basics: testbenches, simulation, and coverage concepts.
• Strong problem-solving skills, attention to detail, and effective communication.
• Ability to work collaboratively on engineering teams and to follow technical guidance from senior engineers.
• Must meet export-control eligibility: U.S. citizen, U.S. national, U.S. permanent resident (Green Card holder), or lawfully admitted as a refugee or granted asylum.
• May be required to pass background checks; some roles may require additional checks (e.g., DBIDS) depending on profile.

Nice-to-have:

• Academic or internship experience with SystemVerilog/UVM.
• Scripting experience (Python, Perl, Tcl) for automation and tooling.
• Coursework or projects in communications systems, DSP, or FPGA design.
• Familiarity with common EDA tools (VCS, Xcelium, Questa, formal tools).
• Understanding of computer architecture fundamentals and bus protocols (e.g., AXI).
• Personal projects, capstone work, or GitHub repositories demonstrating digital design/verification work.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, or a related technical field (completed or in final year) is stated. Coursework or project experience in Verilog/SystemVerilog is expected. (No other formal certifications specified.)

About the Company

Company: Blue Origin

Headquarters: Kent, Washington, United States

Blue Origin is an American aerospace company developing technologies for spaceflight, including reusable launch vehicles, orbital and suborbital systems, and space infrastructure for commercial and government customers.