ASIC Engineer, Design Verification

Job Title

ASIC Engineer, Design Verification

Role Summary

Join the Infrastructure Silicon team to design and verify IP and SoC solutions for data-center applications. The role owns verification closure for modules and sub-systems, including test planning, UVM-based testbench development, and coverage-driven verification.

You will apply simulation, formal, and emulation methodologies, and collaborate with software, hardware, ASIC design, emulation, and post-silicon validation teams to drive first-pass silicon success.

Experience Level

Entry-level (guidance: 2+ years of relevant design verification experience)

Responsibilities

Primary responsibilities include planning and executing functional verification across design hierarchies and improving verification infrastructure and automation.

• Define and implement block, IP, and SoC verification plans to achieve target functional coverage.
• Develop and maintain UVM-based testbenches and verification sequences aligned to the verification plan.
• Drive verification closure using metrics such as functional, code, and assertion coverage.
• Debug and root-cause RTL functional failures and work with ASIC designers to resolve issues.
• Apply formal verification and emulation to complement simulation-based approaches.
• Build reusable verification components (scoreboards, monitors, coverage models).
• Contribute scripting and automation (Python, TCL, Shell) for regressions and flows.
• Participate in design reviews and verification planning to surface risks early.

Requirements

Must-have:

• 2+ years hands-on experience with SystemVerilog and UVM-based verification methodology or equivalent C/C++ hardware verification experience.
• 2+ years experience performing block, IP, sub-system, or SoC-level verification using UVM/OVM methodologies.
• Experience with EDA simulation tools and scripting (Python, TCL, Perl, Shell) for verification environments and flows.
• Experience debugging RTL functional failures and performing root-cause analysis in simulation or emulation environments.

Nice-to-have:

• Experience using emulation platforms for pre-silicon verification.
• Experience verifying ARM or RISC-V based sub-systems or data-center designs (AI/ML accelerators, networking, video processing).
• Experience with IP or integration verification of high-speed interfaces (PCIe, DDR, Ethernet).
• Experience developing UVM environments from scratch (environment architecture, sequencers, coverage models).
• Familiarity with chip debug logic, telemetry, and RAS features.

Education Requirements

Requires a Bachelor's degree in Computer Science, Computer Engineering, or a related technical field (candidates in the process of obtaining a degree are eligible, but the degree must be completed prior to joining). Equivalent practical experience is accepted.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.