ASIC Engineer, Design for Test

Job Title

ASIC Engineer, Design for Test

Role Summary

Work on Meta's Infrastructure Silicon team to define and implement design-for-test (DFT) architectures and flows for large, high-performance ASICs. The role covers RTL-to-silicon DFT strategy, ATPG and memory test, tape-out sign-off, and collaboration with physical design, validation, and manufacturing teams.

Experience Level

Mid-level — typically 6+ years of DFT engineering experience on complex ASIC/SoC designs.

Responsibilities

Deliver DFT solutions and support silicon bring-up across the design lifecycle.

• Define and implement DFT architectures: scan insertion, ATPG, MBIST/LBIST, and boundary scan.
• Develop DFT methodology and RTL-to-tape-out flows, including scan compression, test point insertion, and clock-domain handling.
• Generate, simulate, and validate ATPG patterns to meet fault-coverage targets (stuck-at, transition, path delay, cell-aware).
• Collaborate with physical design to integrate DFT structures within timing, area, and power constraints.
• Partner with silicon validation and manufacturing teams to define ATE test programs and support post-silicon debug and diagnosis.
• Perform DFT sign-off: fault coverage analysis, test reporting, and DRC/LVS compliance for test structures.
• Develop and maintain automation and scripts to streamline DFT flows and reuse across chip generations.
• Support silicon bring-up by analyzing failure data, performing scan diagnosis, and identifying root causes of defects.
• Evaluate and recommend improvements to DFT roadmaps and test strategies.

Requirements

Must-have technical skills and experience required for immediate contribution.

• 6+ years of DFT engineering experience on complex ASIC or SoC designs, including scan insertion, ATPG pattern generation, and MBIST implementation.
• Experience with industry DFT EDA tools (examples: Tessent, Synopsys DFT Compiler, TetraMAX).
• Proven ability to achieve high fault coverage across multiple fault models on large designs.
• Experience supporting silicon bring-up and manufacturing test, including ATE correlation and scan-based diagnosis.
• Scripting experience for DFT automation (Tcl, Python, or Perl).
• Strong collaboration skills with RTL, physical implementation, validation, and manufacturing teams.

Nice-to-have:

• Familiarity with IEEE 1500, IEEE 1687 (IJTAG), or IEEE 1149.1 boundary-scan standards.
• Post-silicon failure analysis and yield-improvement experience using scan diagnosis and statistical defect modeling.
• Experience with at-speed test methods (launch-on-capture/launch-on-shift) and DFT for high-speed SerDes, mixed-signal IP, or hierarchical multi-die/chiplet designs.

Education Requirements

Bachelor's degree in Computer Science, Computer Engineering, or a related technical field is preferred; equivalent practical experience is explicitly accepted.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.