ASIC Engineer, Design

Job Title

ASIC Engineer, Design

Role Summary

The Infra-Silicon team develops custom ASICs for Meta's data center infrastructure to accelerate workloads such as AI inference, video processing, and networking. This role contributes to front-end digital design from microarchitecture through RTL implementation and handoff to physical design teams.

Experience Level

Entry-level / Early Career — typically 2+ years of relevant experience (see Requirements for details).

Responsibilities

Key responsibilities include design, implementation, and cross-team integration of digital ASIC blocks.

• Develop and refine micro-architecture specifications for control, datapath, and interconnect blocks.
• Implement RTL in Verilog or SystemVerilog and ensure code quality and synthesizability.
• Collaborate with verification engineers to review test plans, analyze coverage, and debug functional failures.
• Work with physical design teams to resolve timing, area, and power closure through RTL and constraint changes.
• Integrate soft and hard IP into SoC design flows and participate in design reviews.
• Support emulation and prototyping for early software bring-up and system validation.
• Analyze power and apply low-power techniques such as clock gating and power domain partitioning.
• Translate algorithmic and architecture requirements into implementable hardware micro-architectures.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• Must-have: Minimum 2+ years of digital ASIC or SoC front-end design experience focused on micro-architecture and RTL development.
• Must-have: Proficiency in RTL coding using Verilog or SystemVerilog and experience delivering synthesizable RTL.
• Must-have: Practical experience debugging block- and chip-level issues and collaborating across verification and implementation teams.
• Nice-to-have: Experience with linting, CDC/RDC analysis and flows.
• Nice-to-have: Knowledge of AMBA-AXI, PCIe, or other networking protocols.
• Nice-to-have: Experience with synthesis, static timing analysis, and timing closure methodologies.
• Nice-to-have: Experience designing datapath or memory-subsystem logic for AI, networking, or video workloads.

Education Requirements

Bachelor's degree in Electronics and Communication, Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.