ASIC Engineer

Resquant is looking for highly skilled ASIC Back-End / Physical Design Engineers for various positions. This is a great opportunity to join at an early stage a rapidly growing startup working on the newest trends in chip security and cryptography. The project targets the GlobalFoundries 22 nm FDX (22FDX) FD-SOI platform.

Main responsibilities:

• Driving the full physical implementation flow – floorplanning, placement, clock tree synthesis (CTS) and routing – for quantum resistant cryptographic processors.
• Performing timing closure and static timing analysis (STA) signoff across multiple corners and modes (setup/hold).
• Power planning and analysis, including IR-drop and electromigration (EM) checks.
• Implementing low-power architectures: power domains, level shifters, isolation cells, and the body-bias distribution network required for Adaptive Body Bias (ABB) on GF 22FDX FD-SOI.
• Handling synthesis-to-layout handoff, ECOs, and tapeout preparation in cooperation with the foundry (GlobalFoundries).
• Participation in certification and technical documentation development.

Our requirements:

• Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years (Mid-level) or 8+ years (Senior-level) of hands-on experience in ASIC back-end / physical design.
• Experience with place-and-route tools (e.g. Innovus, IC Compiler II / Fusion Compiler).
• Strong static timing analysis skills and signoff experience (e.g. PrimeTime, Tempus).
• Experience with physical verification tools (e.g. Calibre, IC Validator, Pegasus) for DRC/LVS.
• Proficiency in floorplanning, clock tree synthesis, power planning and routing.
• Knowledge of low-power implementation and power intent (UPF/CPF).
• Understanding of the full ASIC design flow and front-end / back-end interaction.
• Familiarity with high-speed interfaces and protocols such as PCIe, Ethernet, AXI.
• Ability to work independently or strong cooperation skills to work within a cross-functional team.

Preferred candidates with:

• Hands-on experience with the GlobalFoundries 22FDX / FD-SOI process technology.
• Experience with Adaptive Body Bias (ABB) techniques.
• Proven track record in optimization for low power.
• Experience with True Random Number Generators (TRNG) or Physically Unclonable Functions (PUF).
• Experience in side-channel attacks and countermeasures.
• EU/NATO security clearance.
• EU citizenship.

What do we offer:

• Full time Senior and Mid positions in a 3-year project.
• Participation in projects aimed at providing backbone for chip security for dual-use markets.
• Flexible working hours.
• Ability to work remotely (Hybrid/Full).
• Equity options.
• Broad Technical Ownership.
• Innovation and Cutting-Edge Projects.
• Opportunity to attend closed events with military representatives.