ASIC Engineer

Job Title

ASIC Engineer

Role Summary

Join Meta's Silicon Engineering organization to lead performance analysis, pre-silicon modeling, and microarchitectural exploration for custom infrastructure ASICs. The role partners with architecture, RTL, physical design, and software teams to ensure silicon meets throughput, latency, and efficiency targets for hyperscale data center and AI workloads.

Experience Level

Mid-level — typically requires 5+ years of relevant ASIC performance modeling or pre-silicon simulation experience.

Responsibilities

Primary responsibilities focus on defining performance modeling strategy, running pre-silicon simulations, and advising architectural decisions.

• Define and own performance modeling strategy, including cycle-accurate and transaction-level simulation environments.
• Drive microarchitectural exploration and trade-off analysis across compute, memory, interconnect, and I/O domains.
• Develop and validate pre-silicon models that predict post-silicon behavior for data center workloads.
• Establish performance analysis methods, benchmarking frameworks, and bottleneck identification techniques.
• Collaborate with architecture, RTL, and physical design teams to translate performance requirements into microarchitectural specifications.
• Co-optimize software, firmware, and drivers with silicon performance characteristics.
• Lead technical reviews and present modeling results and architectural recommendations to engineering leadership.
• Define long-term performance modeling tooling and automation roadmaps; mentor engineers on simulation and analysis best practices.
• Perform model-to-hardware correlation and structured root-cause analysis to resolve performance gaps.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• 5+ years of experience in ASIC performance modeling, microarchitectural analysis, or pre-silicon simulation for custom silicon or SoC designs.
• Proficiency in C++ and Python for building simulation models, automation frameworks, and analysis tools.
• Experience developing cycle-accurate or transaction-level performance models using C++ and SystemC for processors, memory subsystems, or high-speed interconnects.
• Experience analyzing performance of data center, AI accelerator, or HPC workloads on custom silicon.
• Proven experience defining microarchitectural specifications and driving cross-functional alignment with architecture, RTL, and physical design teams.
• Preferred: post-silicon validation/model-to-hardware correlation, Python automation pipelines for simulation orchestration and regression testing, high-level synthesis and PPA trade-off analysis, experience scaling performance modeling infrastructure, familiarity with SystemVerilog/VHDL and ASIC simulation flows.

Education Requirements

Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.