ASIC Engineer

Job Title

ASIC Engineer

Role Summary

Member of the Global Flows team working on RTL quality and sign-off methodologies for NVIDIA CPU programs. The role bridges digital implementation, microarchitecture, and flow-based checks (CDC, RDC, lint, design auditors, power insertion) to improve RTL quality and silicon readiness.

Work includes methodology development, technical analysis, tool evaluation and deployment, automation, and cross-team coordination with RTL, CAD, verification, and physical-design groups.

Experience Level

Mid-level — typically requires 3+ years of ASIC or SoC RTL design or design-methodology experience.

Responsibilities

Deliver and operationalize RTL design-quality methodologies and support project sign-off criteria.

• Develop and deploy CDC, RDC, lint, netlist/design auditors, power-insertion checks, and related structural analyses.
• Analyze flow results against design intent, perform root-cause analysis across RTL, constraints, tools, and methodology.
• Define quality requirements and readiness criteria; monitor regressions, violation trends, and sign-off status.
• Coordinate and resolve technical issues with RTL build, DFT, clocks/reset, low-power, physical-design, verification, and CAD teams.
• Assess new tool releases and integrate methodology capabilities into project environments.
• Improve runtime, debugging, waiver management, reporting, and training through automation and reusable scripts.

Requirements

Must-have technical skills and experience necessary to perform the role.

• 3+ years of ASIC or SoC RTL design or design-methodology experience.
• Practical experience building, analyzing, and debugging Verilog or SystemVerilog code.
• Strong knowledge of digital design and microarchitecture: pipelines, FSMs, clock/reset architectures, synchronizers, handshakes, asynchronous FIFOs, metastability, and power-domain crossings.
• Experience with front-end methodologies: lint, CDC/RDC, structural RTL analysis, low-power verification, synthesis, or timing constraints.
• Ability to relate methodology results to RTL behavior and perform detailed root-cause analysis.
• Experience in Linux development environments and scripting (Python, Tcl, Perl, shell, or comparable language).

Nice-to-have / Preferred

• Experience with RTL integration, design bring-up, or multi-team debugging at unit, subsystem, chiplet, or SoC scale.
• Familiarity with tools such as Meridian, SpyGlass, VC CDC, Questa CDC, Design Auditor, or power-insertion tools.
• Knowledge of UPF and low-power RTL implementation/verification, SDC, synthesis, static timing analysis, formal verification, or equivalence checking.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.