ASIC DTCO, Timing and Technology Engineer
QualcommJob Title
ASIC DTCO, Timing and Technology Engineer
Role Summary
Perform DTCO (Design-Technology Co-Optimization), timing and technology engineering for SoC blocks and systems targeting mobile, compute, automotive and IoT products on advanced process nodes (5nm–2nm+).
Work with foundry DTCO teams, EDA vendors, CAD and IP teams to validate power/performance, drive Fmax and PPAY improvements, and support process bring-up from PDK to production.
Experience Level
Mid-level. Typical candidates have multiple years of ASIC-related experience; minimum experience requirements vary by degree (see Education Requirements).
Responsibilities
Core responsibilities include analysis, simulation, implementation and cross-team coordination to achieve PPA and process entitlement goals.
- Perform DTCO analysis at block/IP and system level for advanced process technologies.
- Run Spice simulations for power and performance validation (Hspice, Finesim, PrimeSim, AFS, Spectre).
- Perform static timing analysis and signoff using PrimeTime/PT-SI and Tempus.
- Lead block-level PPA analysis and implementation (RTL-to-GDS flow) for hard macros.
- Use synthesis and place-and-route tools (Genus, Innovus, FC Synthesis, FC Place and Route) to optimize Fmax and PPA.
- Collaborate with foundry, EDA partners, CAD and IP teams to drive design convergence and cost/PPAY improvements.
- Support production bring-up of new process technologies and help improve company-wide design convergence processes.
Requirements
Key technical skills and experience required; education details are summarized separately below.
- Must-have: Hands-on experience with Spice simulation environments (Hspice, Finesim, PrimeSim, AFS, Spectre) and STA tools (PrimeTime/PT-SI, Tempus).
- Must-have: Block-level implementation and PPA analysis experience across RTL-to-GDS flows and familiarity with synthesis/place-and-route toolchains (Genus, Innovus, FC flows).
- Must-have: Experience evaluating process technology entitlement and optimizing Fmax, power and area for advanced nodes (5nm–2nm+).
- Must-have: Strong scripting/programming skills: Python, Perl, Tcl, Unix shell; experience with C/C++ is beneficial.
- Must-have: Proven ability to work with foundry DTCO teams, EDA vendors, CAD and IP organizations and to execute design convergence activities.
- Nice-to-have: Experience with ML modeling applied to design or CAD flows.
Education Requirements
Minimum qualifications: Bachelor's degree in Science, Engineering, or a related field plus 4+ years of ASIC design/verification/validation/integration experience; OR Master's degree in Science, Engineering, or related field plus 3+ years; OR PhD in Science, Engineering, or related field plus 2+ years. Fields referenced: science and engineering or related technical disciplines.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
