ASIC Digital Design Verification, Senior Staff Engineer
SynopsysJob Title
ASIC Digital Design Verification, Senior Staff Engineer
Role Summary
Lead RTL verification for ASIC/SoC projects, define verification strategy, and ensure functional correctness from block to chip. Collaborate with RTL designers, synthesis, validation and system teams to deliver production-quality silicon.
Experience Level
Senior-level (Senior Staff Engineer).
Responsibilities
Primary responsibilities include:
- Define and execute block- and chip-level verification plans and schedules.
- Design and maintain SystemVerilog/UVM testbenches and verification IP.
- Develop and run regression suites, maintain CI and automation for verification flows.
- Lead debugging, root-cause analysis, and cross-team issue resolution during bring-up.
- Mentor and review work of verification engineers; provide technical leadership.
Requirements
Must-have and preferred qualifications:
- Extensive ASIC/SoC digital verification experience using SystemVerilog and UVM.
- Hands-on experience with commercial simulators and coverage-driven verification methodologies.
- Strong scripting skills (Python, Perl, or similar) for testbench automation and flows.
- Proven track record in technical leadership or senior contributor roles.
- Nice-to-have: emulation, formal verification, low-power verification, FPGA bring-up, or SoC-level experience.
Education Requirements
Not specified.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
