ASIC Digital Design & Verification Manager
Lead a team responsible for the architecture, design, and verification of synthesizable DesignWare IP cores, with a focus on high-performance memory controller IPs (HBM/DDR/LPDDR).
Work closely with RTL designers, architects, and verification engineers in a global, multi-site organization to deliver production-quality IP and meet release milestones.
Senior — 10–15 years of relevant experience in IP or SoC design and verification; prior experience managing engineering teams.
Accountable for technical leadership and delivery of IP design and verification efforts.
Must-have technical skills, leadership experience, and tooling knowledge.
BS or MS in Electrical Engineering, Electronic Engineering, VLSI, or a closely related technical field. The posting specifies 10–15 years of relevant experience in lieu of additional degree detail.
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
