ASIC Digital Design Staff Engineer

Job Title

ASIC Digital Design Staff Engineer

Role Summary

Design and verify embedded memory test and Silicon Lifecycle Monitor (SLM) IP blocks, delivering RTL, verification environments, DFT integration, and synthesis-ready logic for block and SoC integration. Work within a cross-functional R&D and customer-facing team to define architecture, implement test and analytics features, and provide technical support and training.

This role focuses on practical delivery of robust, high-performance IP and verification solutions for advanced SoC products.

Experience Level

Mid-level — approximately 3–5 years of relevant ASIC digital design and verification experience.

Responsibilities

Primary responsibilities include RTL implementation, verification, DFT, and support for embedded memory test and SLM architectures.

• Develop and model RTL logic (Verilog) for embedded memory test and SLM IP blocks.
• Create and maintain functional verification environments and testbenches at block and SoC levels.
• Perform logic synthesis, static timing analysis, and generate fault coverage and verification reports.
• Apply DFT methodologies for memory and logic testing and resolve timing/DFT functional issues.
• Automate design and verification flows using scripting (Tcl, Python) and build verification infrastructure (UVM/SystemVerilog).
• Define architecture, test plans, and embedded software interfaces; produce protocol documentation and debug guides.
• Collaborate with R&D, product, and customer teams to define features, support product roadmaps, and deliver training and customer support.

Requirements

Required and preferred technical skills and experience.

• Must-have: 3–5 years of ASIC digital design and verification experience; proficiency with RTL simulation, logic synthesis, and timing verification tools.
• Deep expertise with SystemVerilog and UVM; experience in protocol verification for standards such as IEEE1500, IEEE1687, AXI/AMBA.
• Hands-on experience with VIPs, transactors, simulation and emulation flows, and use of EDA tools (examples: VCS, Verdi, Design Compiler/DC).
• Strong DFT knowledge for memory and logic testing and experience producing fault coverage reports.
• Programming and scripting skills: SystemVerilog, Verilog, C/C++, Python, and Tcl for automation.
• Nice-to-have: Experience with cache coherency, advanced interconnects, protocol compliance checking, and working knowledge of emulation/transactor integration.

Education Requirements

Not specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.