ASIC Digital Design Staff Engineer
Lead front-end digital design for LPDDR PHY IP, delivering synthesis-ready RTL and design automation. Work with architecture, verification, analog, and physical design teams to meet timing, power, and area targets for production silicon used in mobile, automotive, and AI products.
Senior level. Posting specifies 5+ years of ASIC digital design experience; role expects demonstrated ownership of RTL in production silicon.
The core responsibilities include front-end RTL design, optimization, and automation:
Must-have technical skills and experience; nice-to-have items listed separately.
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
