ASIC Digital Design Staff Engineer

Job Title

ASIC Digital Design Staff Engineer

Role Summary

Senior verification engineer responsible for end-to-end verification of high-speed interconnect IP (MphyV6, UFS, UniPro) from test planning through coverage closure and sign-off. Work closely with design, architecture, and silicon validation teams to ensure production-quality IP and first-silicon success.

Experience Level

Senior - typically 5+ years experience (with a Bachelor's) or 3+ years (with a Master's) in ASIC verification or related roles.

Responsibilities

Primary duties include planning and executing verification tasks, building robust UVM testbenches, and driving closure to sign-off.

• Own verification for MphyV6, UFS, and UniPro IP blocks from test planning to sign-off.
• Design and extend UVM SystemVerilog testbenches: agents, sequences, scoreboards, coverage models, and protocol checkers.
• Create constrained-random and directed tests targeting corner cases, protocol violations, and timing edges.
• Debug complex failures at waveform, transaction, and protocol levels using Verdi; perform root-cause analysis on RTL and testbench issues.
• Translate protocol specifications into executable test plans, SystemVerilog assertions, and functional coverage.
• Collaborate with designers and validation teams on bug triage, ECO impact analysis, and tape-out readiness.
• Mentor and review work of junior verification engineers; promote UVM best practices.

Requirements

Must-have technical skills and proven experience for immediate contribution.

• Hands-on ASIC verification experience with ownership of IP or subsystem-level blocks.
• Deep expertise in UVM methodology and SystemVerilog, including testbench architecture and coverage-driven verification.
• Strong working knowledge of high-speed interconnect protocols such as UFS, UniPro, MIPI M-PHY, PCIe, or similar.
• Proficiency with Verdi for waveform debug, transaction analysis, and protocol visualization.
• Experience writing SystemVerilog assertions and building functional and code coverage models.
• Demonstrated ability to work independently, drive verification closure, and communicate technical issues across teams.

Nice-to-have:

• Prior experience with tape-out readiness activities and ECO impact analysis.
• Experience building reusable verification infrastructure and tools.

Education Requirements

Bachelor's degree (with 5+ years experience) or Master's degree (with 3+ years experience) in Electronics Engineering, Computer Engineering, or an equivalent technical discipline. Equivalent practical experience in ASIC verification may be considered.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.