ASIC Digital Design Staff Engineer

Job Title

ASIC Digital Design Staff Engineer

Role Summary

Senior verification engineer on the DesignWare IP Verification R&D team based in the Bangalore Design Center. Responsible for building and maintaining UVM/SystemVerilog verification environments and driving verification signoff for IP cores across high-speed interfaces and interconnect protocols.

The role focuses on testbench development, coverage-driven verification, regression management, RTL/testbench debug, and collaboration with global design and verification teams to deliver production-quality IP.

Experience Level

Senior - expects 5+ years of hands-on verification experience for IP cores or SoC designs (Master's with 3+ years also acceptable).

Responsibilities

Primary responsibilities include end-to-end verification of IP cores and test infrastructure maintenance.

• Design and maintain UVM-based verification environments for DesignWare IP (USB, PCIe, Ethernet, AMBA).
• Develop verification strategies and test plans by analyzing specifications and identifying coverage gaps.
• Write SystemVerilog testbenches, constrained-random and directed tests, and functional coverage models.
• Run and manage regressions, analyze coverage reports, and drive closure of functional and code coverage.
• Debug RTL and testbench failures using industry simulators and waveform analysis; collaborate with RTL designers to resolve root causes.
• Integrate and use Verification IP (VIP) to accelerate environment bring-up and testing.
• Contribute to verification methodology improvements and share best practices across a global team.

Requirements

Must-have technical skills and relevant hands-on experience.

• Strong SystemVerilog and HVL coding skills; experience building testbenches and implementing functional coverage.
• Direct experience with UVM, VMM, or OVM methodologies in real verification projects.
• Practical experience with simulators and debug tools such as VCS, Xcelium (NC), or Questa (MTI).
• Solid understanding of functional and code coverage and how to use them to drive verification closure.
• Experience reading and understanding Verilog RTL.
• Familiarity with scripting for automation and regression management (Python or Perl preferred).
• Hands-on experience with at least one industry protocol (USB, PCIe, Ethernet, AMBA) and with integrating VIP.
• Ability to triage regressions, analyze waveforms, and communicate findings clearly to design teams.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering is specified. The posting requests 5+ years of hands-on verification experience for candidates with a Bachelor's, or 3+ years for candidates with a Master's.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.