ASIC Digital Design Staff Engineer

Job Title

ASIC Digital Design Staff Engineer

Role Summary

Senior individual contributor on the DesignWare IP team responsible for RTL design and micro-architecture of high-speed protocol IP (Ethernet, AMBA, PCIe, USB, MIPI, memory controllers) targeting production silicon.

The role requires owning detailed design, driving timing closure, producing readable RTL and documentation, and collaborating across global sites to deliver production-quality IP.

Experience Level

Senior (Staff level). Typical experience: 6+ years ASIC/IP design with a Bachelor's degree or 4+ years with a Master's degree.

Responsibilities

Design and deliver production RTL and architecture for high-speed protocol IP; ensure timing, quality and portability across teams.

• Design and code RTL for high-speed Ethernet and other protocol IP (100G–1.6T), focusing on low latency and timing closure.
• Translate protocol specifications into micro-architecture and detailed design documents for IP blocks.
• Develop and refine directed Verilog/SystemVerilog testbenches to improve functional and code coverage.
• Perform technical reviews of specs, micro-architectures, and RTL across distributed teams.
• Drive timing analysis and closure using synthesis, static timing analysis, lint, CDC, and formal verification flows.
• Apply low-power design techniques and address automotive safety requirements where applicable.
• Collaborate with verification, integration, and product teams across multiple sites to deliver IP on schedule.

Requirements

Must-have technical skills and experience for the role.

• Proven RTL design experience on IP cores or SoC subsystems that have taped out or shipped to customers.
• Hands-on experience with Verilog or SystemVerilog and building directed testbenches.
• Working knowledge of at least one protocol family: AMBA (AHB, AXI, CHI), SD, eMMC, DDR, PCIe, USB, or MIPI; high-speed Ethernet (100G+) is a strong plus.
• Experience with synthesis flows, static timing analysis (STA), lint, CDC analysis, and formal verification tools.
• Ability to produce clear micro-architecture and detailed design documents, especially for control-path designs (async FIFOs, DMA, SRAM/DPRAM interfaces).
• Solid understanding of high-speed, low-latency datapath design and timing-closure challenges.
• Familiarity with Perforce or similar version control and scripting for automation (Perl, shell).
• Strong written communication and code review skills for asynchronous, multi-site collaboration.

Education Requirements

Bachelor's degree in Electrical Engineering (with 6+ years of hands-on ASIC or IP design experience) or a Master's degree in Electrical Engineering (with 4+ years of hands-on ASIC or IP design experience).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.