ASIC Digital Design Staff Engineer

Job Title

ASIC Digital Design Staff Engineer

Role Summary

Design and deliver synthesis-ready RTL for digital blocks and subsystems used in Synopsys IP products. The role partners with verification, implementation, and validation teams to ensure timing, CDC/RDC/lint signoff readiness, and smooth integration across product lines.

Experience Level

Senior (Staff level). Requires 4+ years of experience in digital design and RTL development.

Responsibilities

Primary responsibilities include RTL design, implementation guidance, and cross-team integration.

• Design and implement RTL in Verilog/SystemVerilog for digital blocks and subsystems.
• Refine micro-architecture with attention to synthesizability, timing, testability, area, and power tradeoffs.
• Drive synthesis and front-end implementation activities and support STA/timing-constraint definition.
• Ensure CDC/RDC/Lint readiness and collaborate on design-quality closure.
• Collaborate with verification teams on functional debug, test planning, assertions, and coverage.
• Support debug and issue resolution using Verdi or similar tools and develop automation scripts for design and reporting.
• Participate in design reviews and resolve integration/interoperability issues across product lines.

Requirements

Must-have technical skills and practical experience; separate list for desirable skills.

Must-have:

• 4+ years of experience in digital ASIC design and RTL development.
• Hands-on Verilog/SystemVerilog experience and practical understanding of the ASIC design flow.
• Strong background in synthesis, front-end implementation, and design-for-closure methodology.
• Practical knowledge of STA, timing constraints, and timing arcs.
• Experience with CDC/RDC/Lint concepts and signoff-ready design practices.
• Ability to collaborate effectively with verification, implementation, and validation teams; strong communication skills.
• Scripting experience (Python, Tcl, Perl, or Shell) for automation and productivity improvements.

Nice-to-have:

• Experience with PCIe, USB, or UCIe-based designs.
• Familiarity with Verdi or other waveform/debug tools.
• Exposure to UVM or formal verification concepts.
• Experience with interface IP or protocol bring-up and global product engineering environments.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field (as stated).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.