ASIC Digital Design Sr Staff Engineer

Job Title

ASIC Digital Design Sr Staff Engineer

Role Summary

Lead architect and hands-on implementer of high-performance RTL IP cores for die-to-die communication protocols (UCIe, PCIe, DDR) used in consumer and automotive SoCs. Own micro-architecture, RTL implementation, synthesis, timing closure, and customer integration while mentoring a distributed ASIC design team.

Experience Level

Senior-level engineer; requires 8+ years of hands-on ASIC digital design and RTL implementation experience.

Responsibilities

Primary responsibilities include architecture, implementation, verification coordination, customer interfacing, and team mentorship.

• Architect and implement RTL for high-performance IP cores focused on die-to-die communication.
• Write micro-architecture documents translating functional specifications into implementable design solutions.
• Own the full design flow: SystemVerilog RTL, synthesis, CDC analysis, formal verification, and static timing closure (P&R-aware).
• Collaborate with verification to define testplans, close coverage gaps, and debug corner cases uncovered in regression or customer testing.
• Interface with customers to clarify specifications, align on design intent, and ensure integration requirements are met.
• Mentor and review work of distributed ASIC designers; guide architecture decisions and build team technical depth.
• Drive quality processes including revision control (Perforce), scripting automation (Perl or Shell), and adherence to IP design and reuse standards.

Requirements

Must-have technical skills and demonstrated experience:

• Deep expertise in at least one protocol: UCIe, Ethernet, DDR, PCIe, CXL, or USB, with experience delivering designs from architecture through silicon or customer delivery.
• Strong micro-architecture definition skills and RTL coding in Verilog/SystemVerilog.
• Experience with ASIC design flows: synthesis, CDC analysis, formal checking, and static timing analysis.
• Hands-on experience with high-speed design considerations and P&R-aware synthesis; experience with Fusion Compiler or equivalent EDA tools.
• Proficiency with Perforce and automation scripting (Perl or Shell) for flow development.
• Proven experience technically leading and mentoring ASIC designers, including code and architecture reviews.
• Nice-to-have: familiarity with IP design quality processes, reuse methodologies, and multi-site or customer-facing verification workflows.

Education Requirements

Bachelor's or Master's in Electrical Engineering (BSEE or MSEE) is specified; the posting expects 8+ years of hands-on ASIC digital design experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.