ASIC Digital Design Sr Staff Engineer

Job Title

ASIC Digital Design Sr Staff Engineer

Role Summary

Senior verification engineer responsible for end-to-end functional verification of high-speed interconnect IP (UCIe, PCIe, DDR) used in AI and compute systems. The role focuses on building and maintaining UVM-based testbenches, closing functional coverage tied to silicon risk, and delivering verification sign-off.

Experience Level

Senior; typically requires 7+ years of ASIC/SoC design verification experience with at least 3 years on protocol-heavy IP.

Responsibilities

Primary responsibilities include design, verification, debugging, and mentoring to ensure IP meets silicon-ready quality.

• Own end-to-end verification of UCIe, PCIe, or DDR IP blocks from test planning through coverage closure and sign-off.
• Design and extend UVM testbenches in SystemVerilog: agents, sequencers, scoreboards, coverage models, and protocol checkers.
• Write directed and constrained-random tests that stress protocol compliance, corner cases, and multi-layer interactions.
• Debug complex RTL and testbench failures using Synopsys Verdi or equivalent tools (waveform analysis, protocol trace, transaction debug).
• Translate protocol specifications into executable test plans, SVA assertions, and functional coverage models tied to silicon risks.
• Collaborate with design, architecture, and silicon validation teams on bug triage, ECO impact analysis, and bring-up readiness.
• Mentor verification engineers on UVM methodology, debug techniques, and protocol understanding; contribute to design and verification reviews.

Requirements

Must-have technical skills and experience for immediate contribution.

• 7+ years of hands-on ASIC/SoC design verification experience, with at least 3 years on protocol-heavy IP.
• Deep working knowledge of at least one high-speed protocol: PCIe, UCIe, or DDR; able to read specs and build compliant testbenches.
• Strong UVM methodology experience: building agents, constrained-random sequences, scoreboards, and closing functional coverage.
• Proficient in SystemVerilog including OOP, constrained-random stimulus, and SystemVerilog Assertions (SVA).
• Proven debugging skills with Synopsys Verdi or equivalent (FSDB, protocol analyzers, transaction-level debug).
• Experience with industry simulators such as VCS, Xcelium, or Questa and familiarity with regression and coverage tools (e.g., URG).
• Ability to communicate verification risk and findings clearly to architects and design teams; experience mentoring junior engineers.
• Nice-to-have: working knowledge of a second protocol (PCIe, UCIe, DDR, CXL) and experience contributing reusable verification environments across IP releases.

Education Requirements

B.Tech or M.Tech in Electronics, VLSI, Electrical Engineering, or a related discipline is listed. The posting does not state alternative "equivalent experience" language explicitly.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.