ASIC Digital Design Sr/Staff Engineer

Job Title

ASIC Digital Design Sr/Staff Engineer

Role Summary

Senior engineer responsible for architecting and delivering production-quality RTL IP for high-performance die-to-die communication protocols (e.g. UCIe) for consumer and automotive SoCs. Works across Noida, Bangalore, and San Jose time zones and mentors distributed ASIC design teams.

Experience Level

Senior — requires substantial prior responsibility and technical leadership; posting specifies 8+ years of hands-on ASIC digital design experience.

Responsibilities

Accountable for end-to-end implementation and delivery of IP cores and for mentoring engineers across sites.

• Architect and implement RTL for high-performance IP cores focused on die-to-die protocols (UCIe and related).
• Produce micro-architecture and design documents translating specs into implementable solutions.
• Own full design flow: SystemVerilog RTL, synthesis, CDC analysis, formal checks, and static timing closure (P&R-aware flows).
• Collaborate with verification teams to define testplans, close coverage gaps, and debug regressions and customer issues.
• Interface with customers to clarify specs and ensure integration requirements are met.
• Mentor and lead a distributed team: code reviews, architecture guidance, and skill development.
• Drive quality and automation: revision control (Perforce), scripting (Perl/Shell), and IP reuse standards.

Requirements

Core technical qualifications and leadership skills required; optional items noted separately.

Must-have:

• Proven experience delivering ASIC digital designs and RTL implementations, including micro-architecture definition and SystemVerilog coding.
• Deep expertise in one or more protocols such as UCIe, Ethernet, DDR, PCIe, CXL, or USB with design-to-silicon or customer delivery experience.
• Experience with synthesis, CDC analysis, formal verification, and static timing analysis; familiarity with P&R-aware synthesis techniques and advanced EDA tools (e.g., Fusion Compiler or equivalent).
• Proficiency with Perforce or similar revision control and scripting for automation (Perl, Shell).
• Demonstrated technical leadership and mentoring of ASIC designers, including code reviews and architectural guidance.

Nice-to-have:

• Familiarity with IP design quality processes, reuse methodologies, and multi-site or customer-facing verification workflows.

Education Requirements

BSEE or MSEE in Electrical Engineering. Posting specifies 8+ years of hands-on ASIC digital design and RTL implementation experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.