ASIC Digital Design Senior / Staff Engineer

Job Title

ASIC Digital Design Senior / Staff Engineer

Role Summary

Senior individual contributor responsible for architecting and implementing RTL for high-speed protocol IP (Ethernet, AMBA, PCIe, USB, MIPI, memory controllers) within the DesignWare IP group. The role focuses on producing production-quality RTL, micro-architecture and design documentation, and delivering tapeout-ready IP while collaborating with global teams.

Experience Level

Senior — typically 8+ years hands-on ASIC or IP design experience with a Bachelor's degree, or 6+ years with a Master's degree.

Responsibilities

Primary technical responsibilities for the role include:

• Design and implement RTL for high-speed Ethernet and interconnect IP (100G–1.6T) with emphasis on low latency and timing closure.
• Translate protocol specifications and functional requirements into micro-architecture and detailed design documents for moderate-complexity blocks.
• Develop and refine directed Verilog/SystemVerilog testbenches to improve functional and code coverage and identify real silicon bugs.
• Perform technical reviews of functional specs, micro-architecture documents, and RTL from global design teams.
• Drive timing analysis and closure using synthesis, static timing analysis (STA), lint, CDC, and formal verification flows.
• Apply low-power design techniques and incorporate automotive safety considerations where relevant.
• Collaborate with verification, integration, and product teams across Bangalore and other global sites to deliver IP on schedule.

Requirements

Must-have technical skills and experience:

• Proven RTL design experience on IP cores or SoC subsystems that have taped out or shipped to customers.
• Strong working knowledge of at least one protocol or domain: AMBA (AHB, AXI, CHI), SD/eMMC, DDR, PCIe, USB, MIPI, or memory controllers.
• Ability to create micro-architecture and detailed design documents for control-path designs such as async FIFOs, DMA engines, or SRAM/DPRAM interfaces.
• Hands-on experience with Verilog or SystemVerilog and related simulation and synthesis flows; familiarity with STA, lint, CDC, and formal tools.
• Solid understanding of high-speed, low-latency design techniques and timing closure challenges.
• Familiarity with Perforce (or similar VCS) and scripting for automation (Perl or shell).

Nice-to-have:

• High-speed Ethernet experience (100G and above).
• Datapath or arithmetic algorithm experience (e.g., FEC) and prior work on timing-critical datapaths.
• Experience applying automotive safety requirements to IP development.

Education Requirements

Bachelor's degree in Electrical Engineering with 8+ years of hands-on ASIC or IP design experience, or a Master's degree with 6+ years of experience. Fields mentioned: Electrical Engineering; degree requirements are explicit in the posting.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.